renamed

Author: shtaxxx

examples/thread_mix_verilog_ipcore/Makefile renamed to examples/thread_embedded_verilog_ipcore/Makefile

@@ -1,7 +1,7 @@
 from __future__ import absolute_import
 from __future__ import print_function
 import veriloggen
-import thread_mix_verilog_ipcore
+import thread_embedded_verilog_ipcore
 
 expected_verilog = """
 module test;
@@ -1890,7 +1890,7 @@
 
 def test():
     veriloggen.reset()
-    test_module = thread_mix_verilog_ipcore.mkTest()
+    test_module = thread_embedded_verilog_ipcore.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser

examples/thread_mix_verilog_ipcore/test_thread_mix_verilog_ipcore.py renamed to examples/thread_embedded_verilog_ipcore/test_thread_embedded_verilog_ipcore.py

@@ -1,7 +1,7 @@
 from __future__ import absolute_import
 from __future__ import print_function
 import veriloggen
-import thread_myverilog_ipcore
+import thread_verilog_submodule_ipcore
 
 expected_verilog = """
 module test #
@@ -2084,7 +2084,7 @@
 
 def test():
     veriloggen.reset()
-    test_module = thread_myverilog_ipcore.mkTest()
+    test_module = thread_verilog_submodule_ipcore.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser