Updated the result check codes for the updated iverilog.

Author: shtaxxx

examples/axi_stream_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py

@@ -81,4 +81,3 @@
 
 diff_sum = np.sum(expected - dst)
 print(diff_sum)
-

examples/chatter_clear/test_chatter_clear.py

@@ -185,6 +185,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = chatter_clear.mkTest()

examples/counter/test_counter.py

@@ -90,6 +90,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = counter.mkTest()

examples/led/test_led.py

@@ -82,6 +82,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = led.mkTest()

examples/manyled/manyled.py

@@ -8,6 +8,7 @@
 
 from veriloggen import *
 
+
 def mkLed():
     m = Module('blinkled')
     width = m.Parameter('WIDTH', 8)
@@ -16,8 +17,8 @@ def mkLed():
 
     # function to add an LED port
     def add_led(postfix, limit=1024):
-        led = m.OutputReg('LED'+postfix, width)
-        count = m.Reg('count'+postfix, 32)
+        led = m.OutputReg('LED' + postfix, width)
+        count = m.Reg('count' + postfix, 32)
 
         m.Always(Posedge(clk))(
             If(rst)(
@@ -29,7 +30,7 @@ def add_led(postfix, limit=1024):
                     count(count + 1)
                 )
             ))
-    
+
         m.Always(Posedge(clk))(
             If(rst)(
                 led(0)
@@ -41,10 +42,11 @@ def add_led(postfix, limit=1024):
 
     # call 'add_led' to add LED ports
     for i in range(4):
-        add_led('_' + str(i), limit=i*10 + 10)
-    
+        add_led('_' + str(i), limit=i * 10 + 10)
+
     return m
 
+
 if __name__ == '__main__':
     led = mkLed()
     verilog = led.to_verilog()

examples/manyled/test_manyled.py

@@ -103,6 +103,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = manyled.mkLed()

examples/read_verilog_code/read_verilog_code.py

@@ -43,23 +43,25 @@
 endmodule
 '''
 
+
 def mkLed():
     modules = from_verilog.read_verilog_module_str(led_v)
     m = modules['blinkled']
-    
+
     # change the module name
     m.name = 'modified_led'
-    
+
     # add new statements
     enable = m.Input('enable')
     busy = m.Output('busy')
 
     old_statement = m.always[0].statement[0].false_statement
     m.always[0].statement[0].false_statement = If(enable)(*old_statement)
-    m.Assign( busy(m.variable['count'] < 1023) )
-    
+    m.Assign(busy(m.variable['count'] < 1023))
+
     return m
 
+
 if __name__ == '__main__':
     led = mkLed()
     verilog = led.to_verilog()

examples/read_verilog_code/test_read_verilog_code.py

@@ -40,6 +40,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = read_verilog_code.mkLed()

examples/regchain/regchain.py

@@ -8,6 +8,7 @@
 
 from veriloggen import *
 
+
 def mkRegChain(length=120, width=8):
     m = Module("reg_chain")
 
@@ -19,97 +20,98 @@ def mkRegChain(length=120, width=8):
     seq = Seq(m, 'seq', clk, rst)
 
     update_cond_value = m.TmpReg(3, initval=0)
-    seq( update_cond_value(sw[0:3]) )
+    seq(update_cond_value(sw[0:3]))
 
     area_size = m.TmpReg(2, initval=0)
-    seq( area_size(sw[3:5]) )
-    
+    seq(area_size(sw[3:5]))
+
     count = m.TmpReg(2, initval=0)
-    seq( count.inc() )
-    
+    seq(count.inc())
+
     update_cond = m.TmpReg(initval=0)
-    seq( update_cond(count < update_cond_value) )
+    seq(update_cond(count < update_cond_value))
 
     orig = m.TmpReg(width, initval=0)
     prev = orig
 
     regs = []
-    
+
     for i in range(length):
         area_id = i // (length // 4)
         r = m.TmpReg(width, initval=0)
         regs.append(r)
-        seq.If(AndList(update_cond, area_id <= area_size))( r(prev + 1) )
+        seq.If(AndList(update_cond, area_id <= area_size))(r(prev + 1))
         prev = r
 
-    seq.If(AndList(update_cond, area_size==0))( orig(regs[1*length//4-1] + 3) )
-    seq.If(AndList(update_cond, area_size==1))( orig(regs[2*length//4-1] + 2) )
-    seq.If(AndList(update_cond, area_size==2))( orig(regs[3*length//4-1] + 1) )
-    seq.If(AndList(update_cond, area_size==3))( orig(regs[4*length//4-1] + 0) )
+    seq.If(AndList(update_cond, area_size == 0))(orig(regs[1 * length // 4 - 1] + 3))
+    seq.If(AndList(update_cond, area_size == 1))(orig(regs[2 * length // 4 - 1] + 2))
+    seq.If(AndList(update_cond, area_size == 2))(orig(regs[3 * length // 4 - 1] + 1))
+    seq.If(AndList(update_cond, area_size == 3))(orig(regs[4 * length // 4 - 1] + 0))
 
     seq.make_always()
-    
-    m.Assign( dout(orig) )
+
+    m.Assign(dout(orig))
 
     return m
 
+
 def mkTest(length=120, width=8):
     m = Module('test')
-    
+
     main = mkRegChain(length, width)
     params = m.copy_params(main)
     ports = m.copy_sim_ports(main)
-    
+
     clk = ports['CLK']
     rst = ports['RST']
     sw = ports['sw']
     dout = ports['dout']
 
     fsm = FSM(m, 'fsm', clk, rst)
     count = m.TmpReg(32, initval=0)
-    
-    fsm( sw((3 << 3) | 4) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
-
-    fsm( sw((2 << 3) | 4) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
-
-    fsm( sw((1 << 3) | 4) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
-
-    fsm( sw((0 << 3) | 4) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
-
-    fsm( sw((2 << 3) | 3) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
-
-    fsm( sw((2 << 3) | 2) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
-
-    fsm( sw((2 << 3) | 1) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
-
-    fsm( sw((2 << 3) | 0) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
+
+    fsm(sw((3 << 3) | 4))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
+
+    fsm(sw((2 << 3) | 4))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
+
+    fsm(sw((1 << 3) | 4))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
+
+    fsm(sw((0 << 3) | 4))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
+
+    fsm(sw((2 << 3) | 3))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
+
+    fsm(sw((2 << 3) | 2))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
+
+    fsm(sw((2 << 3) | 1))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
+
+    fsm(sw((2 << 3) | 0))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
 
     fsm.make_always()
-    
+
     uut = m.Instance(main, 'uut',
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
@@ -119,30 +121,31 @@ def mkTest(length=120, width=8):
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 
     nclk = simulation.next_clock
-    
+
     init.add(
         sw(0),
         Delay(1000 * 200),
         Systask('finish'),
     )
 
     return m
-    
+
+
 if __name__ == '__main__':
     main = mkRegChain(length=120)
     verilog = main.to_verilog('tmp.v')
     print(verilog)
 
     #test = mkTest()
     #verilog = test.to_verilog('tmp.v')
-    #print(verilog)
+    # print(verilog)
 
     # run simulator (Icarus Verilog)
     #sim = simulation.Simulator(test)
-    #rslt = sim.run() # display=False
+    # rslt = sim.run() # display=False
     ##rslt = sim.run(display=True)
-    #print(rslt)
+    # print(rslt)
 
     # launch waveform viewer (GTKwave)
-    #sim.view_waveform() # background=False
-    #sim.view_waveform(background=True)
+    # sim.view_waveform() # background=False
+    # sim.view_waveform(background=True)

examples/regchain/test_regchain.py

@@ -650,6 +650,7 @@
 endmodule
 """
 
+
 def test():
     veriloggen.reset()
     test_module = regchain.mkRegChain(length=120)