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Applied autopep8
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8 files changed

+75
-74
lines changed

8 files changed

+75
-74
lines changed

‎veriloggen/core/vtypes.py‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,7 @@ def get_value(obj):
151151
return obj.value
152152
return None
153153

154+
154155
def get_initval(obj):
155156
if hasattr(obj, 'initval'):
156157
return obj.initval

‎veriloggen/pipeline/pipeline.py‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ def __init__(self, m, name, clk, rst, width=32):
6363

6464
self.done = False
6565

66-
#-------------------------------------------------------------------------
66+
# -------------------------------------------------------------------------
6767
def input(self, data, valid=None, ready=None, width=None):
6868
if ready is not None and not isinstance(ready, (vtypes.Wire, vtypes.Output)):
6969
raise TypeError('ready port of PipelineVariable must be Wire., not %s' %
@@ -73,7 +73,7 @@ def input(self, data, valid=None, ready=None, width=None):
7373
self.vars.append(ret)
7474
return ret
7575

76-
#-------------------------------------------------------------------------
76+
# -------------------------------------------------------------------------
7777
# self.__call__() calls this method
7878
def stage(self, data, initval=0, width=None, preg=None):
7979
if width is None:
@@ -96,7 +96,7 @@ def stage(self, data, initval=0, width=None, preg=None):
9696

9797
return ret
9898

99-
#-------------------------------------------------------------------------
99+
# -------------------------------------------------------------------------
100100
# Accumulator
101101
def acc_and(self, data, initval=0, resetcond=None, width=None):
102102
return self._accumulate([vtypes.And], data, width, initval, resetcond)
@@ -146,7 +146,7 @@ def acc_custom(self, data, ops, initval=0, resetcond=None, width=None, label=Non
146146
ops = [ops]
147147
return self._accumulate(ops, data, width, initval, resetcond, label)
148148

149-
#-------------------------------------------------------------------------
149+
# -------------------------------------------------------------------------
150150
def make_always(self, reset=(), body=()):
151151
if self.done:
152152
raise ValueError('make_always() has been already called.')
@@ -165,19 +165,19 @@ def make_always(self, reset=(), body=()):
165165
self.make_code()
166166
))
167167

168-
#-------------------------------------------------------------------------
168+
# -------------------------------------------------------------------------
169169
def make_reset(self):
170170
return self.seq.make_reset()
171171

172-
#-------------------------------------------------------------------------
172+
# -------------------------------------------------------------------------
173173
def make_code(self):
174174
return self.seq.make_code()
175175

176-
#-------------------------------------------------------------------------
176+
# -------------------------------------------------------------------------
177177
def draw_graph(self, filename='out.png', prog='dot'):
178178
_draw_graph(self, filename, prog)
179179

180-
#-------------------------------------------------------------------------
180+
# -------------------------------------------------------------------------
181181
def _accumulate(self, ops, data, width=None, initval=0, resetcond=None, oplabel=None):
182182
if width is None:
183183
width = self.width
@@ -197,7 +197,7 @@ def _accumulate(self, ops, data, width=None, initval=0, resetcond=None, oplabel=
197197

198198
return ret
199199

200-
#-------------------------------------------------------------------------
200+
# -------------------------------------------------------------------------
201201
def _add_reg(self, prefix, count, width=None, initval=0):
202202
tmp_name = '_'.join(['', self.name, prefix, str(count)])
203203
tmp = self.m.Reg(tmp_name, width, initval=initval)
@@ -208,7 +208,7 @@ def _add_wire(self, prefix, count, width=None):
208208
tmp = self.m.Wire(tmp_name, width)
209209
return tmp
210210

211-
#-------------------------------------------------------------------------
211+
# -------------------------------------------------------------------------
212212
def _make_tmp(self, data, valid, ready, width=None, initval=0, acc_ops=()):
213213
tmp_data = self._add_reg(
214214
'data', self.tmp_count, width=width, initval=initval)
@@ -298,7 +298,7 @@ def _make_tmp(self, data, valid, ready, width=None, initval=0, acc_ops=()):
298298

299299
return tmp_data, tmp_valid, tmp_ready
300300

301-
#-------------------------------------------------------------------------
301+
# -------------------------------------------------------------------------
302302
def _make_prev(self, data, valid, ready, width=None, initval=0):
303303
tmp_data = self._add_reg(
304304
'data', self.tmp_count, width=width, initval=initval)
@@ -320,11 +320,11 @@ def _make_prev(self, data, valid, ready, width=None, initval=0):
320320

321321
return tmp_data, tmp_valid, tmp_ready
322322

323-
#-------------------------------------------------------------------------
323+
# -------------------------------------------------------------------------
324324
def __call__(self, data, initval=0, width=None):
325325
return self.stage(data, initval=initval, width=width)
326326

327-
#-------------------------------------------------------------------------
327+
# -------------------------------------------------------------------------
328328

329329

330330
class _PipelineInterface(object):
@@ -339,7 +339,7 @@ def __str__(self):
339339
args = [self.data, self.valid, self.ready]
340340
return ','.join([str(arg) for arg in args])
341341

342-
#-------------------------------------------------------------------------
342+
# -------------------------------------------------------------------------
343343

344344

345345
class _PipelineNumeric(vtypes._Numeric):
@@ -451,7 +451,7 @@ def _get_preg(self, stage_id):
451451
return self
452452
return self.preg_dict[stage_id]
453453

454-
#-------------------------------------------------------------------------
454+
# -------------------------------------------------------------------------
455455

456456

457457
class _PipelineVisitor(object):
@@ -520,7 +520,7 @@ def visit_str(self, node):
520520
def visit_float(self, node):
521521
raise NotImplementedError('visit__Constant() must be implemented')
522522

523-
#-------------------------------------------------------------------------
523+
# -------------------------------------------------------------------------
524524

525525

526526
class DataVisitor(_PipelineVisitor):
@@ -655,7 +655,7 @@ def visit_str(self, node):
655655
def visit_float(self, node):
656656
return (None, vtypes.Float(node), None, [])
657657

658-
#-------------------------------------------------------------------------
658+
# -------------------------------------------------------------------------
659659

660660

661661
def _draw_graph(df, filename='out.png', prog='dot'):

‎veriloggen/stream/visitor.py‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@ def visit__Accumulator(self, node):
111111
reset = (self.visit(node.reset)
112112
if node.reset is not None else set())
113113
reg_initval = (self.visit(node.reg_initval)
114-
if node.reg_initval is not None else set())
114+
if node.reg_initval is not None else set())
115115
return right | size | interval | initval | offset | dependency | enable | reset | reg_initval
116116

117117
def visit__ParameterVariable(self, node):
@@ -163,7 +163,7 @@ def visit__Accumulator(self, node):
163163
reset = (self.visit(node.reset)
164164
if node.reset is not None else set())
165165
reg_initval = (self.visit(node.reg_initval)
166-
if node.reg_initval is not None else set())
166+
if node.reg_initval is not None else set())
167167
mine = set([node]) if node._has_output() else set()
168168
return right | size | interval | initval | offset | dependency | enable | reset | reg_initval | mine
169169

@@ -219,7 +219,7 @@ def visit__Accumulator(self, node):
219219
reset = (self.visit(node.reset)
220220
if node.reset is not None else set())
221221
reg_initval = (self.visit(node.reg_initval)
222-
if node.reg_initval is not None else set())
222+
if node.reg_initval is not None else set())
223223
mine = set([node])
224224
return right | size | interval | initval | offset | dependency | enable | reset | reg_initval | mine
225225

‎veriloggen/thread/axistreamout.py‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
5858
'write_local_stride_fifo']),
5959
self.addrwidth)
6060
self.write_size_fifo = self.m.Wire('_'.join(['', self.name,
61-
'write_size_fifo']),
61+
'write_size_fifo']),
6262
self.addrwidth + 1)
6363

6464
write_unpack_values = self.unpack_write_req(self.write_req_fifo.rdata)
@@ -539,7 +539,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
539539
'write_op_sel_fifo']),
540540
self.op_sel_width)
541541
self.write_size_fifo = self.m.Wire('_'.join(['', self.name,
542-
'write_size_fifo']),
542+
'write_size_fifo']),
543543
self.addrwidth + 1)
544544

545545
write_unpack_values = self.unpack_write_req(self.write_req_fifo.rdata)
@@ -615,7 +615,7 @@ def _set_write_request(self, fifo, start, size):
615615
vtypes.Not(self.write_req_fifo.almost_full))
616616

617617
_ = self.write_req_fifo.enq_rtl(self.pack_write_req(op_id,
618-
local_size),
618+
local_size),
619619
cond=enq_cond)
620620

621621
def _synthesize_write_data_fsm(self, fifo, fifo_datawidth):
@@ -669,7 +669,7 @@ def _synthesize_write_data_fsm_same(self, fifo, fifo_datawidth):
669669

670670
# Data state 1
671671
cur_rvalid = self.m.TmpWire(prefix='cur_rvalid')
672-
#rready = vtypes.Ands(vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)),
672+
# rready = vtypes.Ands(vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)),
673673
# self.write_size_buf > 0)
674674
rready = vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid))
675675
deq_cond = vtypes.Ands(data_fsm.here, vtypes.Not(fifo.empty),
@@ -751,7 +751,7 @@ def _synthesize_write_data_fsm_narrow(self, fifo, fifo_datawidth):
751751

752752
# Data state 1
753753
cur_rvalid = self.m.TmpWire(prefix='cur_rvalid')
754-
#rready = vtypes.Ands(vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)),
754+
# rready = vtypes.Ands(vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid)),
755755
# self.write_size_buf > 0)
756756
rready = vtypes.Ors(self.tdata.tready, vtypes.Not(self.tdata.tvalid))
757757
deq_cond = vtypes.Ands(data_fsm.here, vtypes.Not(fifo.empty),

‎veriloggen/thread/ram.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -948,7 +948,7 @@ def __init__(self, src=None, name=None, keep_hierarchy=False):
948948
if not isinstance(ram, MultibankRAM) and isinstance(first, MultibankRAM):
949949
raise ValueError('RAM type must be same')
950950
if (isinstance(ram, MultibankRAM) and isinstance(first, MultibankRAM) and
951-
ram.numbanks != first.numbanks):
951+
ram.numbanks != first.numbanks):
952952
raise ValueError('numbanks must be same')
953953

954954
self.m = src[0].m

‎veriloggen/thread/thread.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,7 @@ def ret(self, fsm):
174174

175175
return self.return_value
176176

177-
#--------------------------------------------------------------------------
177+
# --------------------------------------------------------------------------
178178
def add_function(self, func):
179179
name = func.__name__
180180
if name in self.function_lib:

‎veriloggen/types/ipxact.py‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -53,9 +53,9 @@ def to_ipxact(m, ip_name=None, ip_ver='1.0',
5353

5454
if not os.path.exists(dirname):
5555
os.mkdir(dirname)
56-
#if not os.path.exists(dirname + '/' + 'data'):
56+
# if not os.path.exists(dirname + '/' + 'data'):
5757
# os.mkdir(dirname + '/' + 'data')
58-
#if not os.path.exists(dirname + '/' + 'bd'):
58+
# if not os.path.exists(dirname + '/' + 'bd'):
5959
# os.mkdir(dirname + '/' + 'bd')
6060
if not os.path.exists(dirname + '/' + 'xgui'):
6161
os.mkdir(dirname + '/' + 'xgui')
@@ -109,19 +109,19 @@ def to_ipxact(m, ip_name=None, ip_ver='1.0',
109109
f.write(xml_code)
110110
f.close()
111111

112-
## xdc
112+
# xdc
113113
#xdc_code = open(TEMPLATE_DIR + 'ipxact.xdc', 'r').read()
114114

115115
#f = open(xdcpath + xdcname, 'w')
116-
#f.write(xdc_code)
117-
#f.close()
116+
# f.write(xdc_code)
117+
# f.close()
118118

119-
## bd
119+
# bd
120120
#bd_code = open(TEMPLATE_DIR + 'bd.tcl', 'r').read()
121121

122122
#f = open(bdpath + bdname, 'w')
123-
#f.write(bd_code)
124-
#f.close()
123+
# f.write(bd_code)
124+
# f.close()
125125

126126
# xgui file
127127
xgui_code = open(TEMPLATE_DIR + 'xgui_tcl.txt', 'r').read()

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