stream.read_RAM with when condition.

Author: shtaxxx

tests/extension/thread_/stream_read_ram_when/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/thread_/stream_read_ram_when/test_thread_stream_read_ram_when.py

@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_read_ram_when
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_read_ram_when.run(filename=None, simtype=simtype,
+                                           outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')

tests/extension/thread_/stream_read_ram_when/thread_stream_read_ram_when.py

@@ -0,0 +1,147 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+
+    ram_ext = vthread.RAM(m, 'ram_ext', clk, rst, datawidth, addrwidth, numports=2)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+
+    a = strm.source('a')
+    r_addr = a
+
+    r = strm.read_RAM('ext', r_addr, when=r_addr & 0x1 == 1)
+    b = r + 100
+
+    strm.sink(b, 'b')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_sink('b', ram_b, offset, size)
+        strm.set_read_RAM('ext', ram_ext)
+        strm.run()
+        strm.join()
+
+    def comp_sequential(size, offset):
+        r = 0
+        for i in range(size):
+            r_addr = ram_a.read(i)
+            if r_addr & 0x1 == 1:
+                r = ram_ext.read(r_addr)
+            b = r + 100
+            ram_b.write(i + offset, b)
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_b.read(i + offset_stream)
+            sq = ram_b.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        for i in range(size):
+            ram_a.write(i, size - i - 1)
+
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_ext, offset, 0, size)
+        comp_stream(size, offset)
+        myaxi.dma_write(ram_b, offset, 1024, size)
+
+        # sequential
+        offset = size * 4
+        myaxi.dma_read(ram_ext, offset, 0, size)
+        comp_sequential(size, offset)
+        myaxi.dma_write(ram_b, offset, 1024 * 2, size)
+
+        # verification
+        check(size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)

veriloggen/stream/stypes.py

@@ -3169,11 +3169,17 @@ def _implement(self, m, seq, svalid=None, senable=None):
         self.sig_data = data
 
 
-class ReadRAM(_BinaryOperator):
+class ReadRAM(_SpecialOperator):
     latency = 3
 
-    def __init__(self, addr, reset, width=None, point=None, signed=True, ram_name=None):
-        _BinaryOperator.__init__(self, addr, reset)
+    def __init__(self, addr, reset, when=None,
+                 width=None, point=None, signed=True, ram_name=None):
+
+        args = [addr, reset]
+        if when is not None:
+            args.append(when)
+
+        _SpecialOperator.__init__(self, *args)
 
         if width is not None:
             self.width = width
@@ -3191,6 +3197,9 @@ def _implement(self, m, seq, svalid=None, senable=None):
             raise ValueError("Latency mismatch '%d' < '%s'" %
                              (self.latency, 2))
 
+        if len(self.args) == 3 and self.latency == 2:
+            raise ValueError('Output register is required for when option')
+
         if senable is not None:
             raise NotImplementedError('senable is not supported.')
 
@@ -3206,29 +3215,40 @@ def _implement(self, m, seq, svalid=None, senable=None):
         elif self.latency == 3:
             data = m.Reg(self.name('data'), datawidth, initval=0, signed=signed)
             self.sig_data = data
-            seq(data(rdata), cond=senable)
+            when_cond = self.args[2].sig_data if len(self.args) == 3 else None
+            if when_cond is not None:
+                when_cond = seq.Prev(when_cond, 2)
+            enable = _and_vars(senable, when_cond)
+            seq(data(rdata), cond=enable)
 
         else:
             prev_data = None
 
+            when_cond_base = self.args[2].sig_data if len(self.args) == 3 else None
+
             for i in range(self.latency - 2):
                 data = m.Reg(self.name('data_d%d' % i), datawidth,
                              initval=0, signed=signed)
+                if when_cond_base is not None:
+                    when_cond = seq.Prev(when_cond, i + 2)
+                else:
+                    when_cond = None
+                enable = _and_vars(senable, when_cond)
                 if i == 0:
-                    seq(data(rdata), cond=senable)
+                    seq(data(rdata), cond=enable)
                 else:
-                    seq(data(prev_data), cond=senable)
+                    seq(data(prev_data), cond=enable)
                 prev_data = data
 
             self.sig_data = data
 
     @property
     def addr(self):
-        return self.left.sig_data
+        return self.args[0].sig_data
 
     @property
     def enable(self):
-        return vtypes.Not(self.right.sig_data)
+        return vtypes.Not(self.args[1].sig_data)
 
 
 def make_condition(*cond, **kwargs):

veriloggen/thread/stream.py

@@ -336,7 +336,9 @@ def substream(self, substrm):
         self.substreams.append(sub)
         return sub
 
-    def read_RAM(self, name, addr, datawidth=None, point=0, signed=True):
+    def read_RAM(self, name, addr, when=None,
+                 datawidth=None, point=0, signed=True):
+
         if self.stream_synthesized:
             raise ValueError(
                 'cannot modify the stream because already synthesized')
@@ -356,7 +358,8 @@ def read_RAM(self, name, addr, datawidth=None, point=0, signed=True):
         if datawidth is None:
             datawidth = self.datawidth
 
-        var = self.ReadRAM(addr, width=datawidth, point=point, signed=signed, ram_name=name)
+        var = self.ReadRAM(addr, when=when,
+                           width=datawidth, point=point, signed=signed, ram_name=name)
 
         self.read_rams[name] = var
         self.var_id_map[_id] = var