ReadRAM is upgraded like the combination of Variable and RAM, so that RAM assignments are configurable at runtime.

Author: shtaxxx

tests/extension/thread_/stream_read_ram/thread_stream_read_ram.py

@@ -30,14 +30,15 @@ def mkLed():
     a = strm.source('a')
     r_addr = a
 
-    r = strm.ReadRAM(ram_ext, r_addr, port=1)
+    r = strm.read_RAM('ext', r_addr)
     b = r + 100
 
     strm.sink(b, 'b')
 
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size)
         strm.set_sink('b', ram_b, offset, size)
+        strm.set_read_RAM('ext', ram_ext)
         strm.run()
         strm.join()
 

veriloggen/stream/stypes.py

@@ -3169,48 +3169,66 @@ def _implement(self, m, seq, svalid=None, senable=None):
         self.sig_data = data
 
 
-class ReadRAM(_UnaryOperator):
-    latency = 1
-
-    def __init__(self, ram, addr, width=None, point=None, signed=True, port=0):
-        _UnaryOperator.__init__(self, addr)
+class ReadRAM(_BinaryOperator):
+    latency = 3
 
-        self.ram = ram
+    def __init__(self, addr, reset, width=None, point=None, signed=True, ram_name=None):
+        _BinaryOperator.__init__(self, addr, reset)
 
-        if width is None:
-            self.width = ram.datawidth
-        else:
+        if width is not None:
             self.width = width
 
-        if point is None:
-            self.point = 0 if not hasattr(ram, 'point') else ram.point
-        else:
+        if point is not None:
             self.point = point
 
         self.signed = signed
-        self.port = port
 
-        self.graph_label = 'Read ' + ram.name if hasattr(ram, 'name') else 'Read RAM'
+        self.graph_label = 'ReadRAM' if ram_name is None else ('ReadRAM\n%s' % ram_name)
         self.graph_shape = 'box'
 
     def _implement(self, m, seq, svalid=None, senable=None):
+        if self.latency < 2:
+            raise ValueError("Latency mismatch '%d' < '%s'" %
+                             (self.latency, 2))
+
+        if senable is not None:
+            raise NotImplementedError('senable is not supported.')
+
         datawidth = self.bit_length()
-        addrwidth = int(log(self.ram.length, 2))
         signed = self.get_signed()
-
         rdata = m.Wire(self.name('rdata'), datawidth, signed=signed)
+        self.read_data = rdata
 
-        raddr = m.Wire(self.name('raddr'), addrwidth)
-        raddr.assign(self.right.sig_data)
+        if self.latency == 2:
+            data = m.Wire(self.name('data'), datawidth, signed=signed)
+            self.sig_data = data
+
+        elif self.latency == 3:
+            data = m.Reg(self.name('data'), datawidth, initval=0, signed=signed)
+            self.sig_data = data
+            seq(data(rdata), cond=senable)
 
-        if hasattr(self.ram, 'connect'):
-            self.ram.connect(self.port, raddr, 0, 0)
-            rdata.assign(self.ram.rdata(self.port))
+        else:
+            prev_data = None
 
-        elif hasattr(self.ram, 'connect_rtl'):
-            self.ram.connect_rtl(self.port, raddr, 0, 0, rdata)
+            for i in range(self.latency - 2):
+                data = m.Reg(self.name('data_d%d' % i), datawidth,
+                             initval=0, signed=signed)
+                if i == 0:
+                    seq(data(rdata), cond=senable)
+                else:
+                    seq(data(prev_data), cond=senable)
+                prev_data = data
 
-        self.sig_data = rdata
+            self.sig_data = data
+
+    @property
+    def addr(self):
+        return self.left.sig_data
+
+    @property
+    def enable(self):
+        return vtypes.Not(self.right.sig_data)
 
 
 def make_condition(*cond, **kwargs):

veriloggen/thread/stream.py

@@ -43,6 +43,7 @@ class Stream(BaseStream):
                       'set_sink', 'set_sink_pattern', 'set_sink_multidim',
                       'set_sink_multipattern', 'set_sink_immediate',
                       'set_sink_empty', 'set_constant',
+                      'set_read_RAM',
                       'read_sink',
                       'run', 'join', 'done',
                       'source_join', 'source_done',
@@ -100,6 +101,7 @@ def __init__(self, m, name, clk, rst,
         self.sinks = OrderedDict()
         self.constants = OrderedDict()
         self.substreams = []
+        self.read_rams = OrderedDict()
 
         self.var_name_map = OrderedDict()
         self.var_id_map = OrderedDict()
@@ -334,6 +336,40 @@ def substream(self, substrm):
         self.substreams.append(sub)
         return sub
 
+    def read_RAM(self, name, addr, datawidth=None, point=0, signed=True):
+        if self.stream_synthesized:
+            raise ValueError(
+                'cannot modify the stream because already synthesized')
+
+        _id = self.var_id_count
+        if name is None:
+            name = 'read_ram_%d' % _id
+
+        if name in self.var_name_map:
+            raise ValueError("'%s' is already defined in stream '%s'" %
+                             (name, self.name))
+
+        prefix = self._prefix(name)
+
+        self.var_id_count += 1
+
+        if datawidth is None:
+            datawidth = self.datawidth
+
+        var = self.ReadRAM(addr, width=datawidth, point=point, signed=signed, ram_name=name)
+
+        self.read_rams[name] = var
+        self.var_id_map[_id] = var
+        self.var_name_map[name] = var
+        self.var_id_name_map[_id] = name
+        self.var_name_id_map[name] = _id
+
+        var.read_ram_id_map = OrderedDict()
+        var.read_ram_sel = self.module.Reg('_%s_read_ram_sel' % prefix,
+                                           self.ram_sel_width, initval=0)
+
+        return var
+
     def set_source(self, fsm, name, ram, offset, size, stride=1, port=0):
         """ intrinsic method to assign RAM property to a source stream """
 
@@ -906,6 +942,35 @@ def set_constant(self, fsm, name, value, raw=False):
 
         fsm.goto_next()
 
+    def set_read_RAM(self, fsm, name, ram, port=0):
+        """ intrinsic method to assign RAM property to a read-RAM interface """
+
+        if not self.stream_synthesized:
+            self._implement_stream()
+
+        if isinstance(name, str):
+            var = self.var_name_map[name]
+        elif isinstance(name, vtypes.Str):
+            name = name.value
+            var = self.var_name_map[name]
+        elif isinstance(name, int):
+            var = self.var_id_map[name]
+        elif isinstance(name, vtypes.Int):
+            name = name.value
+            var = self.var_id_map[name]
+        else:
+            raise TypeError('Unsupported index name')
+
+        if name not in self.read_rams:
+            raise NameError("No such stream '%s'" % name)
+
+        set_cond = self._set_flag(fsm)
+
+        port = vtypes.to_int(port)
+        self._setup_read_ram(ram, var, port, set_cond)
+
+        fsm.goto_next()
+
     def read_sink(self, fsm, name):
         """ intrinsic method to read the last output of a sink stream """
 
@@ -2110,6 +2175,119 @@ def _synthesize_set_sink_multipattern(self, var, name):
                                  var.sink_multipat_num_patterns == 0).goto_init()
         var.sink_multipat_fsm.If(self.term_sink).goto_init()
 
+    def _setup_read_ram(self, ram, var, port, set_cond):
+        if ram._id() in var.read_ram_id_map:
+            ram_id = var.read_ram_id_map[ram._id()]
+            self.seq.If(set_cond)(
+                var.read_ram_sel(ram_id)
+            )
+            return
+
+        if ram._id() not in self.ram_id_map:
+            ram_id = self.ram_id_count
+            self.ram_id_count += 1
+            self.ram_id_map[ram._id()] = ram_id
+        else:
+            ram_id = self.ram_id_map[ram._id()]
+
+        var.read_ram_id_map[ram._id()] = ram_id
+
+        self.seq.If(set_cond)(
+            var.read_ram_sel(ram_id)
+        )
+
+        ram_cond = (var.read_ram_sel == ram_id)
+        renable = vtypes.Ands(var.enable, ram_cond)
+
+        d, v = ram.read_rtl(var.addr, port=port, cond=renable)
+        add_mux(var.read_data, ram_cond, d)
+
+        if (self.dump and
+            (self.dump_mode == 'all' or
+                 self.dump_mode == 'ram' or
+             (self.dump_mode == 'selective' and
+                 hasattr(ram, 'dump') and ram.dump))):
+            self._setup_read_ram_dump(ram, var, renable, d)
+
+    def _setup_read_ram_dump(self, ram, var, read_enable, read_data):
+        pipeline_depth = self.pipeline_depth()
+        log_pipeline_depth = max(
+            int(math.ceil(math.log(max(pipeline_depth, 10), 10))), 1)
+
+        addr_base = (ram.dump_addr_base if hasattr(ram, 'dump_addr_base') else
+                     self.dump_base)
+        addr_base_char = ('b' if addr_base == 2 else
+                          'o' if addr_base == 8 else
+                          'd' if addr_base == 10 else
+                          'x')
+        addr_prefix = ('0b' if addr_base == 2 else
+                       '0o' if addr_base == 8 else
+                       '  ' if addr_base == 10 else
+                       '0x')
+        addr_vfmt = ''.join([addr_prefix, '%', addr_base_char])
+
+        data_base = (ram.dump_data_base if hasattr(ram, 'dump_data_base') else
+                     self.dump_base)
+        data_base_char = ('b' if data_base == 2 else
+                          'o' if data_base == 8 else
+                          'd' if (data_base == 10 and
+                                  (not hasattr(ram, 'point') or ram.point <= 0)) else
+                          # 'f' if (data_base == 10 and
+                          #        hasattr(ram, 'point') and ram.point > 0) else
+                          'g' if (data_base == 10 and
+                                  hasattr(ram, 'point') and ram.point > 0) else
+                          'x')
+        data_prefix = ('0b' if data_base == 2 else
+                       '0o' if data_base == 8 else
+                       '  ' if data_base == 10 else
+                       '0x')
+        # if data_base_char == 'f':
+        #    point_len = int(math.ceil(ram.point / math.log(10, 2)))
+        #    point_len = max(point_len, 8)
+        #    total_len = int(math.ceil(ram.datawidth / math.log(10, 2)))
+        #    total_len = max(total_len, point_len)
+        #    data_vfmt = ''.join([data_prefix, '%',
+        #                         '%d.%d' % (total_len + 1, point_len),
+        #                         data_base_char])
+        # else:
+        #    data_vfmt = ''.join([data_prefix, '%', data_base_char])
+        data_vfmt = ''.join([data_prefix, '%', data_base_char])
+
+        name = ram.name
+        fmt = ''.join(['(', self.name, ' step:%d, ',
+                       'read, ', ' ' * (log_pipeline_depth + 2),
+                       'age:%d) ', name,
+                       '[', addr_vfmt, '] = ', data_vfmt])
+
+        dump_ram_step_name = ('_stream_dump_ram_step_%d_%s' %
+                              (self.object_id, name))
+        dump_ram_step = self.module.Reg(dump_ram_step_name, 32, initval=0)
+
+        enable = self.seq.Prev(read_enable, 2)
+        age = dump_ram_step
+        addr = self.seq.Prev(var.addr, 2)
+        if hasattr(ram, 'point') and ram.point > 0:
+            data = vtypes.Div(vtypes.SystemTask('itor', read_data),
+                              1.0 * (2 ** ram.point))
+        elif hasattr(ram, 'point') and ram.point < 0:
+            data = vtypes.Times(read_data, 2 ** -ram.point)
+        else:
+            data = read_data
+
+        self.seq(
+            dump_ram_step(0)
+        )
+        self.seq.If(enable)(
+            dump_ram_step.inc()
+        )
+        self.seq.If(self.dump_enable)(
+            dump_ram_step.inc()
+        )
+
+        self.seq.If(enable, vtypes.Not(self.dump_mask))(
+            vtypes.Display(fmt, dump_ram_step, age, addr, data)
+        )
+
     def _set_flag(self, fsm, prefix='_set_flag'):
         flag = self.module.TmpReg(initval=0, prefix=prefix)
         cond = fsm.here
@@ -2166,7 +2344,8 @@ def __getattr__(self, attr):
              f.__name__.startswith('Counter') or
              f.__name__.startswith('Pulse') or
              f.__name__.startswith('RingBuffer') or
-             f.__name__.startswith('Scratchpad'))):
+             f.__name__.startswith('Scratchpad') or
+             f.__name__.startswith('ReadRAM'))):
             if self.reduce_reset is None:
                 self.reduce_reset = self.module.Reg(
                     '_'.join(['', self.name, 'reduce_reset']), initval=1)