visit_Instance() in from_verilog.read_verilog_module returns an Instance object with a child Module definition, not StubModule.

Author: shtaxxx

tests/verilog/read_verilog_/branchpredunit/read_verilog_branchpredunit.py

@@ -16,5 +16,5 @@ def mkMips():
 
 if __name__ == '__main__':
     mips_modules = mkMips()
-    verilog = ''.join([ m.to_verilog() for m in mips_modules.values() ])
+    verilog = ''.join([ m.to_verilog() for m in mips_modules.values() if not m.used ])
     print(verilog)

tests/verilog/read_verilog_/branchpredunit/test_read_verilog_branchpredunit.py

@@ -537,7 +537,7 @@
 def test():
     veriloggen.reset()
     test_modules = read_verilog_branchpredunit.mkMips()
-    code = ''.join([ m.to_verilog() for m in test_modules.values() ])
+    code = ''.join([ m.to_verilog() for m in test_modules.values() if not m.used ])
 
     from pyverilog.vparser.parser import parse
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator

tests/verilog/read_verilog_/module_initial/read_verilog_module_initial.py

@@ -12,11 +12,10 @@
 def mkLedTest():
     filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v'
     modules = from_verilog.read_verilog_module(filename)
-    led = modules['blinkled']
     test = modules['test']
-    return led, test
+    return test
 
 if __name__ == '__main__':
-    led, test = mkLedTest()
-    verilog = ''.join([ test.to_verilog(), led.to_verilog() ])
+    test = mkLedTest()
+    verilog = test.to_verilog()
     print(verilog)

tests/verilog/read_verilog_/module_initial/test_read_verilog_module_initial.py

@@ -81,8 +81,8 @@
 
 def test():
     veriloggen.reset()
-    test_module, test_bench = read_verilog_module_initial.mkLedTest()
-    code = ''.join([ test_bench.to_verilog(), test_module.to_verilog() ])
+    test_module = read_verilog_module_initial.mkLedTest()
+    code = test_module.to_verilog()
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
     parser = VerilogParser()

tests/verilog/read_verilog_/pycoram_object/read_verilog_pycoram_object.py

@@ -17,5 +17,5 @@ def mkUserlogic():
 
 if __name__ == '__main__':
     modules = mkUserlogic()
-    verilog = ''.join([ m.to_verilog() for m in modules.values() ])
+    verilog = ''.join([ m.to_verilog() for m in modules.values() if not m.used ])
     print(verilog)

tests/verilog/read_verilog_/pycoram_object/test_read_verilog_pycoram_object.py

@@ -4,27 +4,6 @@
 import read_verilog_pycoram_object
 
 expected_verilog = """
-module CoramMemory1P #
-(
-  parameter CORAM_THREAD_NAME = "undefined",
-  parameter CORAM_THREAD_ID = 0,
-  parameter CORAM_ID = 0,
-  parameter CORAM_SUB_ID = 0,
-  parameter CORAM_ADDR_LEN = 10,
-  parameter CORAM_DATA_WIDTH = 32
-)
-(
-  input CLK,
-  input [CORAM_ADDR_LEN - 1:0] ADDR,
-  input [CORAM_DATA_WIDTH - 1:0] D,
-  input WE,
-  output [CORAM_DATA_WIDTH - 1:0] Q
-);
-
-  localparam CORAM_MEM_SIZE = (2 ** CORAM_ADDR_LEN);
-
-endmodule
-
 module CoramMemoryBE1P #
 (
   parameter CORAM_THREAD_NAME = "undefined",
@@ -145,32 +124,6 @@
 
 endmodule
 
-module CoramChannel #
-(
-  parameter CORAM_THREAD_NAME = "undefined",
-  parameter CORAM_THREAD_ID = 0,
-  parameter CORAM_ID = 0,
-  parameter CORAM_SUB_ID = 0,
-  parameter CORAM_ADDR_LEN = 4,
-  parameter CORAM_DATA_WIDTH = 32
-)
-(
-  input CLK,
-  input RST,
-  input [CORAM_DATA_WIDTH - 1:0] D,
-  input ENQ,
-  output FULL,
-  output ALM_FULL,
-  output [CORAM_DATA_WIDTH - 1:0] Q,
-  input DEQ,
-  output EMPTY,
-  output ALM_EMPTY
-);
-
-  localparam CORAM_MEM_SIZE = (2 ** CORAM_ADDR_LEN);
-
-endmodule
-
 module CoramRegister #
 (
   parameter CORAM_THREAD_NAME = "undefined",
@@ -293,13 +246,60 @@
     .EMPTY(comm_empty)
   );
 
+endmodule
+
+module CoramMemory1P #
+(
+  parameter CORAM_THREAD_NAME = "undefined",
+  parameter CORAM_THREAD_ID = 0,
+  parameter CORAM_ID = 0,
+  parameter CORAM_SUB_ID = 0,
+  parameter CORAM_ADDR_LEN = 10,
+  parameter CORAM_DATA_WIDTH = 32
+)
+(
+  input CLK,
+  input [CORAM_ADDR_LEN - 1:0] ADDR,
+  input [CORAM_DATA_WIDTH - 1:0] D,
+  input WE,
+  output [CORAM_DATA_WIDTH - 1:0] Q
+);
+
+  localparam CORAM_MEM_SIZE = (2 ** CORAM_ADDR_LEN);
+
+endmodule
+
+module CoramChannel #
+(
+  parameter CORAM_THREAD_NAME = "undefined",
+  parameter CORAM_THREAD_ID = 0,
+  parameter CORAM_ID = 0,
+  parameter CORAM_SUB_ID = 0,
+  parameter CORAM_ADDR_LEN = 4,
+  parameter CORAM_DATA_WIDTH = 32
+)
+(
+  input CLK,
+  input RST,
+  input [CORAM_DATA_WIDTH - 1:0] D,
+  input ENQ,
+  output FULL,
+  output ALM_FULL,
+  output [CORAM_DATA_WIDTH - 1:0] Q,
+  input DEQ,
+  output EMPTY,
+  output ALM_EMPTY
+);
+
+  localparam CORAM_MEM_SIZE = (2 ** CORAM_ADDR_LEN);
+
 endmodule
 """
 
 def test():
     veriloggen.reset()
     modules = read_verilog_pycoram_object.mkUserlogic()
-    code = ''.join([ m.to_verilog() for m in modules.values() ])
+    code = ''.join([ m.to_verilog() for m in modules.values() if not m.used ])
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator

veriloggen/core/module.py

@@ -33,6 +33,7 @@ def __init__(self, name=None, tmp_prefix='_tmp'):
         self.tmp_prefix = tmp_prefix
         self.tmp_count = 0
         self.hook = []
+        self.used = False
 
     #---------------------------------------------------------------------------
     # User interface for variables
@@ -798,6 +799,7 @@ def __init__(self, name=None, code=''):
         vtypes.VeriloggenNode.__init__(self)
         self.name = name if name is not None else self.__class__.__name__
         self.code = code
+        self.used = False
 
     def set_code(self, code):
         self.code = code
@@ -833,6 +835,8 @@ def __init__(self, module, instname, params=None, ports=None):
         self._type_check_ports(ports)
         self.module = module
         self.instname = instname
+        if hasattr(self.module, 'used'):
+            self.module.used = True
 
         if not params:
             self.params = ()

veriloggen/verilog/from_verilog.py

@@ -31,9 +31,10 @@ def read_verilog_stubmodule(*filelist, **opt):
 
 def read_verilog_module(*filelist, **opt):
     module_dict = to_module_dict(*filelist, **opt)
-    visitor = VerilogReadVisitor()
-    modules = collections.OrderedDict([ (name, visitor.visit(m) )
-                                        for name, m in module_dict.items() ])
+    visitor = VerilogReadVisitor(module_dict)
+    for name, m in module_dict.items():
+        visitor.visit(m)
+    modules = visitor.converted_modules
     return modules
 
 def read_verilog_module_str(code, encode='utf-8'):
@@ -101,10 +102,25 @@ def __getattr__(self, attr):
 
 #-------------------------------------------------------------------------------
 class VerilogReadVisitor(object):
-    def __init__(self):
+    def __init__(self, ast_module_dict, converted_modules=None):
+        self.ast_module_dict = ast_module_dict
+        self.converted_modules = (collections.OrderedDict()
+                                  if converted_modules is None
+                                  else converted_modules)
         self.m = None
         self.module_stack = []
 
+    def get_module(self, name):
+        if name in self.converted_modules:
+            return self.converted_modules[name]
+        if name not in self.ast_module_dict:
+            return StubModule(name)
+        visitor = VerilogReadVisitor(self.ast_module_dict, self.converted_modules)
+        mod = visitor.visit(self.ast_module_dict[name])
+        self.converted_modules[name] = mod
+        self.converted_modules.update(visitor.converted_modules)
+        return mod
+
     def push_module(self, m):
         self.module_stack.append(self.m)
         self.m = m
@@ -132,11 +148,17 @@ def visit(self, node):
         return visitor(node)
 
     def visit_ModuleDef(self, node):
+        # check module cache
+        if node.name in self.converted_modules:
+            return self.converted_modules[node.name]
+
         # create new Verilog module
         m = module.Module(node.name)
         self.push_module(m)
         self.generic_visit(node)
         self.pop_module()
+
+        self.converted_modules[node.name] = m
         return m
 
     def visit_Paramlist(self, node):
@@ -684,7 +706,7 @@ def visit_InstanceList(self, node):
         return [ self.visit(instance) for instance in node.instances ]
 
     def visit_Instance(self, node):
-        m = module.StubModule(node.module)
+        m = self.get_module(node.module)
         instname = node.name
         params = [ self.visit(param) for param in node.parameterlist ]
         ports = [ self.visit(port) for port in node.portlist ]