from_verilog.read_verilog_stubmodule() returns StubModules with the original codes.

Author: shtaxxx

tests/verilog/read_verilog_/stub_module/test_read_verilog_stub_module.py

@@ -24,6 +24,38 @@
    LED
   );
 endmodule
+
+module blinkled #
+  (
+   parameter WIDTH = 8
+  )
+  (
+   input CLK, 
+   input RST, 
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+  always @(posedge CLK) begin
+    if(RST) begin        
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end 
+  end 
+  always @(posedge CLK) begin
+    if(RST) begin        
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin        
+        LED <= LED + 1;
+      end  
+    end 
+  end 
+endmodule
 """
 
 def test():

tests/verilog/read_verilog_/stub_module_str/test_read_verilog_stub_module_str.py

@@ -24,6 +24,38 @@
    LED
   );
 endmodule
+
+module blinkled #
+  (
+   parameter WIDTH = 8
+  )
+  (
+   input CLK, 
+   input RST, 
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+  always @(posedge CLK) begin
+    if(RST) begin        
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end 
+  end 
+  always @(posedge CLK) begin
+    if(RST) begin        
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin        
+        LED <= LED + 1;
+      end  
+    end 
+  end 
+endmodule
 """
 
 def test():

veriloggen/verilog/from_verilog.py

@@ -13,14 +13,20 @@
 import pyverilog.vparser.ast as vast
 from pyverilog.vparser.parser import VerilogCodeParser
 from pyverilog.dataflow.modulevisitor import ModuleVisitor
+from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
 
 #-------------------------------------------------------------------------------
 # User interfaces to read Verilog source code
 #-------------------------------------------------------------------------------
 def read_verilog_stubmodule(*filelist, **opt):
     module_dict = to_module_dict(*filelist, **opt)
-    stubs = collections.OrderedDict([ (name, module.StubModule(name)) 
-                                      for name in module_dict.keys() ])
+    codegen = ASTCodeGenerator()
+    stubs = collections.OrderedDict()
+    for name, m in module_dict.items():
+        description = vast.Description( (m,) )
+        source = vast.Source('', description)
+        code = codegen.visit(source)
+        stubs[name] = module.StubModule(name, code=code)
     return stubs
 
 def read_verilog_module(*filelist, **opt):