ObjectLike methods are implemented.

shtaxxx · shtaxxx · commit 952ba9fd2d9b · 2015-11-29T23:43:06.000+09:00
diff --git a/tests/core/like/Makefile b/tests/core/like/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd
diff --git a/tests/core/like/like.py b/tests/core/like/like.py
@@ -0,0 +1,70 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    
+    led = m.Output('LED', width)
+    count = m.Reg('count', 32)
+
+    # reg with same name
+    _led = m.RegLike(led)
+    
+    # output with same name
+    _count = m.OutputLike(count)
+
+    # signals with different name
+    width1 = m.ParameterLike(width, name='WIDTH1')
+    width2 = m.LocalparamLike(width, name='WIDTH2')
+    
+    input_count = m.OutputLike(count, name='input_count')
+    output_count = m.OutputLike(count, name='output_count')
+    wire_count = m.WireLike(count, name='wire_count')
+    reg_count = m.RegLike(count, name='reg_count', initval=8)
+
+    m.Assign( wire_count(input_count) )
+    m.Assign( output_count(reg_count) )
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            m.make_reset()
+        ).Else(
+            reg_count(wire_count)
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + 1)
+            )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(0)
+        ).Else(
+            If(count == 1023)(
+                led(led + 1)
+            )
+        ))
+
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    verilog = led.to_verilog()
+    print(verilog)
diff --git a/tests/core/like/test_like.py b/tests/core/like/test_like.py
@@ -0,0 +1,69 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import like
+
+expected_verilog = """
+module blinkled #
+ (
+  parameter WIDTH = 8,
+  parameter WIDTH1 = 8
+ )
+ (
+  input CLK, 
+  input RST, 
+  output reg [WIDTH-1:0] LED,
+  output reg [32-1:0] count,
+  output [32-1:0] input_count,
+  output [32-1:0] output_count
+ );
+
+  localparam WIDTH2 = 8;
+
+  wire [32-1:0] wire_count;
+  reg [32-1:0] reg_count;
+  assign wire_count = input_count;
+  assign output_count = reg_count;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      reg_count <= 8;
+    end else begin
+      reg_count <= wire_count;
+    end
+  end
+
+  always @(posedge CLK) begin
+    if(RST) begin        
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end 
+  end 
+  always @(posedge CLK) begin
+    if(RST) begin        
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin        
+        LED <= LED + 1;
+      end  
+    end 
+  end 
+endmodule
+"""
+
+def test():
+    test_module = like.mkLed()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)
diff --git a/veriloggen/core/module.py b/veriloggen/core/module.py
@@ -156,6 +156,104 @@ def TmpLocalparam(self, value, width=None, signed=False, length=None):
         self.tmp_count += 1
         return self.Localparam(name, value, width, signed, length)
 
+    #---------------------------------------------------------------------------
+    def InputLike(self, src, name=None, width=None, length=None, signed=None, value=None):
+        if name is None: name = src.name
+        if width is None: width = src.width
+        #if length is None: length = src.length
+        if length is None: length = None
+        if signed is None: signed = src.signed
+        if value is None: value = src.value
+        return self.Input(name, width, length, signed, value)
+        
+    def OutputLike(self, src, name=None, width=None, length=None, signed=None, value=None):
+        if name is None: name = src.name
+        if width is None: width = src.width
+        #if length is None: length = src.length
+        if length is None: length = None
+        if signed is None: signed = src.signed
+        if value is None: value = src.value
+        return self.Output(name, width, length, signed, value)
+        
+    def OutputRegLike(self, src, name=None, width=None, length=None, signed=None, value=None, initval=None):
+        if name is None: name = src.name
+        if width is None: width = src.width
+        #if length is None: length = src.length
+        if length is None: length = None
+        if signed is None: signed = src.signed
+        if value is None: value = src.value
+        if initval is None: initval = src.initval
+        return self.OutputReg(name, width, length, signed, value, initval)
+        
+    def InoutLike(self, src, name=None, width=None, length=None, signed=None, value=None):
+        if name is None: name = src.name
+        if width is None: width = src.width
+        #if length is None: length = src.length
+        if length is None: length = None
+        if signed is None: signed = src.signed
+        if value is None: value = src.value
+        return self.Inout(name, width, length, signed, value)
+        
+    def WireLike(self, src, name=None, width=None, length=None, signed=None, value=None):
+        if name is None: name = src.name
+        if width is None: width = src.width
+        if length is None: length = src.length
+        if signed is None: signed = src.signed
+        if value is None: value = src.value
+        return self.Wire(name, width, length, signed, value)
+        
+    def RegLike(self, src, name=None, width=None, length=None, signed=None, value=None, initval=None):
+        if name is None: name = src.name
+        if width is None: width = src.width
+        if length is None: length = src.length
+        if signed is None: signed = src.signed
+        if value is None: value = src.value
+        if initval is None: initval = src.initval
+        return self.Reg(name, width, length, signed, value, initval)
+
+    def IntegerLike(self, src, name=None, width=None, length=None, signed=None, value=None, initval=None):
+        if name is None: name = src.name
+        if width is None: width = src.width
+        if length is None: length = src.length
+        if signed is None: signed = src.signed
+        if value is None: value = src.value
+        if initval is None: initval = src.initval
+        return self.Integer(name, width, length, signed, value, initval)
+
+    def RealLike(self, src, name=None, width=None, length=None, signed=None, value=None, initval=None):
+        if name is None: name = src.name
+        if width is None: width = src.width
+        if length is None: length = src.length
+        if signed is None: signed = src.signed
+        if value is None: value = src.value
+        if initval is None: initval = src.initval
+        return self.Real(name, width, length, signed, value, initval)
+
+    def GenvarLike(self, src, name=None, width=None, length=None, signed=None, value=None):
+        if name is None: name = src.name
+        if width is None: width = src.width
+        #if length is None: length = src.length
+        if length is None: length = None
+        if signed is None: signed = src.signed
+        if value is None: value = src.value
+        return self.Genvar(name, width, length, signed, value)
+
+    def ParameterLike(self, src, name=None, value=None, width=None, signed=False, length=None):
+        if name is None: name = src.name
+        if value is None: value = src.value
+        if width is None: width = src.width
+        if signed is None: signed = src.signed
+        if length is None: length = src.length
+        return self.Parameter(name, value, width, signed, length)
+    
+    def LocalparamLike(self, src, name=None, value=None, width=None, signed=False, length=None):
+        if name is None: name = src.name
+        if value is None: value = src.value
+        if width is None: width = src.width
+        if signed is None: signed = src.signed
+        if length is None: length = src.length
+        return self.Localparam(name, value, width, signed, length)
+    
     #---------------------------------------------------------------------------
     # User interface for control statements
     #---------------------------------------------------------------------------
