Mux is an alias of Cond.

Author: shtaxxx

tests/core/mux/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

tests/core/mux/mux.py

@@ -0,0 +1,38 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            count( Mux(count==1023, 0, count + 1) )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(0)
+        ).Else(
+            led( Mux(count==1024-1, led+1, led) )
+        ))
+    
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    verilog = led.to_verilog('')
+    print(verilog)

tests/core/mux/test_mux.py

@@ -0,0 +1,44 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import mux
+
+expected_verilog = """
+module blinkled #
+  ( 
+   parameter WIDTH = 8
+  )
+  ( 
+   input CLK, 
+   input RST,
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      count <= (count == 1023)? 0 : count + 1;
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      LED <= (count == 1023)? LED + 1 : LED;
+    end
+  end
+endmodule
+"""
+
+def test():
+    test_module = mux.mkLed()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

veriloggen/core/vtypes.py

@@ -726,6 +726,9 @@ def bit_length(self):
 
     def __str__(self):
         return ''.join(['(', str(self.condition), ')?', str(self.true_value), ' : ', str(self.false_value)])
+
+# Alias of Cond
+Mux = Cond
 
 #-------------------------------------------------------------------------------
 class Sensitive(VeriloggenNode):