Updated README

Author: shtaxxx

README.md

@@ -77,7 +77,6 @@ Requirements
 --------------------
 
 - Python3: 3.6 or later
-
 - Icarus Verilog: 10.1 or later
 
 ```
@@ -92,23 +91,27 @@ sudo apt install iverilog
 pip3 install pyverilog jinja2 numpy
 ```
 
-Optional Installation
+Optional installation for testing
 --------------------
 
+These are required for the testing execution of test codes in tests and examples.
+We recommend to these testing library to verify the under development behavior.
+
 - pytest: 3.2 or later
 - pytest-pythonpath: 0.7 or later
 
-These are required for the testing execution of test codes in tests and examples.
-
 ```
 pip3 install pytest pytest-pythonpath
 ```
 
+Optional installation for visualization
+--------------------
+
+To visualize the generated hardware by veriloggen.stream, these libraries are required.
+
 - Graphviz: 2.38.0 or later
 - Pygraphviz: 1.3.1 or later
 
-These are required for graph visualization by veriloggen.dataflow:
-
 ```
 sudo apt install graphviz
 pip3 install pygraphviz
@@ -117,7 +120,7 @@ pip3 install pygraphviz
 Install
 --------------------
 
-Install Veriloggen:
+Now you can install Veriloggen using setup.py script.
 
 ```
 python3 setup.py install
@@ -137,7 +140,7 @@ make
 ```
 
 
-Getting Started
+Getting started
 ==============================
 
 You can find some examples in 'veriloggen/examples/' and 'veriloggen/tests'.
@@ -338,16 +341,16 @@ If you installed GTKwave and enable 'sim.view_waveform()' in 'hello_led.py', you
 ![waveform.png](img/waveform.png)
 
 
-Veriloggen Extension Libraries
+Veriloggen extension libraries
 ==============================
 
-Mixed-Paradigm High-Level Synthesis
+Mixed-paradigm high-level synthesis
 --------------------
 
 - veriloggen.thread.Thread: Procedural high-level synthesis for DMA and I/O controls
 - veriloggen.thread.Stream: Dataflow-based high-level synthesis for high-performance stream processing
 
-Frequently-used Abstractions
+Frequently-used abstractions
 --------------------
 
 - veriloggen.verilog: Verilog HDL source code synthesis and import APIs
@@ -358,7 +361,7 @@ Frequently-used Abstractions
 Please see examples and tests directories for many examples.
 
 
-Related Project
+Related project
 ==============================
 
 [Pyverilog](https://github.com/PyHDI/Pyverilog)

README.rst

@@ -90,7 +90,6 @@ Requirements
 ------------
 
 -  Python3: 3.6 or later
-
 -  Icarus Verilog: 10.1 or later
 
 ::
@@ -105,24 +104,29 @@ Requirements
 
    pip3 install pyverilog jinja2 numpy
 
-Optional Installation
----------------------
+Optional installation for testing
+---------------------------------
+
+These are required for the testing execution of test codes in tests and
+examples. We recommend to these testing library to verify the under
+development behavior.
 
 -  pytest: 3.2 or later
 -  pytest-pythonpath: 0.7 or later
 
-These are required for the testing execution of test codes in tests and
-examples.
-
 ::
 
    pip3 install pytest pytest-pythonpath
 
+Optional installation for visualization
+---------------------------------------
+
+To visualize the generated hardware by veriloggen.stream, these
+libraries are required.
+
 -  Graphviz: 2.38.0 or later
 -  Pygraphviz: 1.3.1 or later
 
-These are required for graph visualization by veriloggen.dataflow:
-
 ::
 
    sudo apt install graphviz
@@ -131,7 +135,7 @@ These are required for graph visualization by veriloggen.dataflow:
 Install
 -------
 
-Install Veriloggen:
+Now you can install Veriloggen using setup.py script.
 
 ::
 
@@ -151,7 +155,7 @@ without any installation on your host platform.
    cd veriloggen/examples/led/
    make
 
-Getting Started
+Getting started
 ===============
 
 You can find some examples in ‘veriloggen/examples/’ and
@@ -359,18 +363,18 @@ If you installed GTKwave and enable ‘sim.view_waveform()’ in
 
    waveform.png
 
-Veriloggen Extension Libraries
+Veriloggen extension libraries
 ==============================
 
-Mixed-Paradigm High-Level Synthesis
+Mixed-paradigm high-level synthesis
 -----------------------------------
 
 -  veriloggen.thread.Thread: Procedural high-level synthesis for DMA and
    I/O controls
 -  veriloggen.thread.Stream: Dataflow-based high-level synthesis for
    high-performance stream processing
 
-Frequently-used Abstractions
+Frequently-used abstractions
 ----------------------------
 
 -  veriloggen.verilog: Verilog HDL source code synthesis and import APIs
@@ -380,7 +384,7 @@ Frequently-used Abstractions
 
 Please see examples and tests directories for many examples.
 
-Related Project
+Related project
 ===============
 
 `Pyverilog <https://github.com/PyHDI/Pyverilog>`__ - Python-based