Merge branch 'feature_update_predicate_reg' into develop

Author: shtaxxx

veriloggen/stream/stypes.py

@@ -3172,8 +3172,7 @@ def write(self, fsm, value):
         )
 
 
-class Reg(_SpecialOperator):
-    __intrinsics__ = ('write')
+class Predicate(_SpecialOperator):
     latency = 1
 
     def __init__(self, data, when=None):
@@ -3188,7 +3187,7 @@ def __init__(self, data, when=None):
         self.point = data.get_point()
         self.signed = data.get_signed()
 
-        self.graph_label = 'Reg'
+        self.graph_label = 'Predicate'
         self.graph_shape = 'box'
 
     def _implement(self, m, seq, svalid=None, senable=None):
@@ -3210,6 +3209,15 @@ def _implement(self, m, seq, svalid=None, senable=None):
 
         seq(data(arg_data[0]), cond=enable)
 
+
+class Reg(Predicate):
+    __intrinsics__ = ('write')
+
+    def __init__(self, data, when=None):
+        Predicate.__init__(self, data, when)
+        self.graph_label = 'Reg'
+        self.graph_shape = 'box'
+
     def write(self, fsm, value):
         cond = fsm.here
 
@@ -3218,18 +3226,6 @@ def write(self, fsm, value):
         )
 
 
-class Predicate(Reg):
-    __intrinsics__ = ()
-
-    def __init__(self, data, when):
-        Reg.__init__(self, data, when)
-        self.graph_label = 'Predicate'
-        self.graph_shape = 'box'
-
-    def write(self, fsm, value):
-        raise NotImplementedError()
-
-
 class ReadRAM(_SpecialOperator):
     latency = 3