lib_pipeline_ test is updated.

shtaxxx · shtaxxx · commit 833678edf185 · 2015-10-30T12:21:09.000+09:00
diff --git a/tests/lib_pipeline_/acc_add/lib_pipeline_acc_add.py b/tests/lib_pipeline_/acc_add/lib_pipeline_acc_add.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/acc_add/test_lib_pipeline_acc_add.py b/tests/lib_pipeline_/acc_add/test_lib_pipeline_acc_add.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_acc_add
 
 expected_verilog = """
 module test;
@@ -142,8 +142,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_acc_add.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_pipeline_/acc_add_valid/lib_pipeline_acc_add_valid.py b/tests/lib_pipeline_/acc_add_valid/lib_pipeline_acc_add_valid.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/acc_add_valid/test_lib_pipeline_acc_add_valid.py b/tests/lib_pipeline_/acc_add_valid/test_lib_pipeline_acc_add_valid.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_acc_add_valid
 
 expected_verilog = """
 module test;
@@ -145,8 +145,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_acc_add_valid.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_pipeline_/acc_add_validready/lib_pipeline_acc_add_validready.py b/tests/lib_pipeline_/acc_add_validready/lib_pipeline_acc_add_validready.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/acc_add_validready/test_lib_pipeline_acc_add_validready.py b/tests/lib_pipeline_/acc_add_validready/test_lib_pipeline_acc_add_validready.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_acc_add_validready
 
 expected_verilog = """
 module test;
@@ -255,8 +255,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_acc_add_validready.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_pipeline_/multi_input/lib_pipeline_multi_input.py b/tests/lib_pipeline_/multi_input/lib_pipeline_multi_input.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/multi_input/test_lib_pipeline_multi_input.py b/tests/lib_pipeline_/multi_input/test_lib_pipeline_multi_input.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_multi_input
 
 expected_verilog = """
 module test;
@@ -296,8 +296,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_multi_input.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_pipeline_/multi_output/lib_pipeline_multi_output.py b/tests/lib_pipeline_/multi_output/lib_pipeline_multi_output.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/multi_output/test_lib_pipeline_multi_output.py b/tests/lib_pipeline_/multi_output/test_lib_pipeline_multi_output.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_multi_output
 
 expected_verilog = """
 module test;
@@ -470,8 +470,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_multi_output.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_pipeline_/select/lib_pipeline_select.py b/tests/lib_pipeline_/select/lib_pipeline_select.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/select/test_lib_pipeline_select.py b/tests/lib_pipeline_/select/test_lib_pipeline_select.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_select
 
 expected_verilog = """
 module test;
@@ -296,8 +296,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_select.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_pipeline_/single_add/lib_pipeline_single_add.py b/tests/lib_pipeline_/single_add/lib_pipeline_single_add.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/single_add/test_lib_pipeline_single_add.py b/tests/lib_pipeline_/single_add/test_lib_pipeline_single_add.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_single_add
 
 expected_verilog = """
 module test;
@@ -144,8 +144,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_single_add.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_pipeline_/single_add_valid/lib_pipeline_single_add_valid.py b/tests/lib_pipeline_/single_add_valid/lib_pipeline_single_add_valid.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/single_add_valid/test_lib_pipeline_single_add_valid.py b/tests/lib_pipeline_/single_add_valid/test_lib_pipeline_single_add_valid.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_single_add_valid
 
 expected_verilog = """
 module test;
@@ -188,8 +188,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_single_add_valid.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_pipeline_/single_add_validready/lib_pipeline_single_add_validready.py b/tests/lib_pipeline_/single_add_validready/lib_pipeline_single_add_validready.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/single_add_validready/test_lib_pipeline_single_add_validready.py b/tests/lib_pipeline_/single_add_validready/test_lib_pipeline_single_add_validready.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_single_add_validready
 
 expected_verilog = """
 module test;
@@ -293,8 +293,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_single_add_validready.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_pipeline_/single_passthrough/lib_pipeline_single_passthrough.py b/tests/lib_pipeline_/single_passthrough/lib_pipeline_single_passthrough.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/single_passthrough/test_lib_pipeline_single_passthrough.py b/tests/lib_pipeline_/single_passthrough/test_lib_pipeline_single_passthrough.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_single_passthrough
 
 expected_verilog = """
 module test;
@@ -241,8 +241,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_single_passthrough.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_pipeline_/unbalanced_output/lib_pipeline_unbalanced_output.py b/tests/lib_pipeline_/unbalanced_output/lib_pipeline_unbalanced_output.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_pipeline_/unbalanced_output/test_lib_pipeline_unbalanced_output.py b/tests/lib_pipeline_/unbalanced_output/test_lib_pipeline_unbalanced_output.py
@@ -1,4 +1,4 @@
-import led
+import lib_pipeline_unbalanced_output
 
 expected_verilog = """
 module test;
@@ -397,8 +397,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_pipeline_unbalanced_output.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
