Bug fix of AXI-Lite Master/Slave: AXI-Lite interface must not issue/accept any request until the preivous request is successfully completed.

Author: shtaxxx

veriloggen/thread/axim.py

@@ -1837,7 +1837,8 @@ def read(self, fsm, global_addr):
         fsm.If(ack).goto_next()
 
         # state 1
-        fsm.goto_next()
+        done = vtypes.Ands(self.raddr.arvalid, self.raddr.arready)
+        fsm.If(done).goto_next()
 
         # state 2
         rcond = fsm.here
@@ -1863,7 +1864,8 @@ def write(self, fsm, global_addr, value):
         fsm.If(ack).goto_next()
 
         # state 1
-        fsm.goto_next()
+        done = vtypes.Ands(self.waddr.awvalid, self.waddr.awready)
+        fsm.If(done).goto_next()
 
         # state 2
         wcond = fsm.here
@@ -1872,13 +1874,18 @@ def write(self, fsm, global_addr, value):
         ack = vtypes.Ors(self.wdata.wready, vtypes.Not(self.wdata.wvalid))
         fsm.If(ack).goto_next()
 
-    def write_fence(self, fsm, global_addr, value):
-
-        self.write(fsm, global_addr, value)
+        # state 3
+        done = vtypes.Ands(self.wdata.wvalid, self.wdata.wready)
+        fsm.If(done).goto_next()
 
+        # state 4
         res = self.write_completed()
         fsm.If(res).goto_next()
 
+    def write_fence(self, fsm, global_addr, value):
+        """ AXI-Lite Master must not issue any request until the previous request is completed."""
+        self.write(fsm, global_addr, value)
+
     def set_global_base_addr(self, fsm, addr):
 
         if not self.use_global_base_addr:
@@ -1909,12 +1916,16 @@ def read_delayed(self, fsm, global_addr, delay):
         fsm.If(ack).goto_next()
 
         # state 1
+        done = vtypes.Ands(self.raddr.arvalid, self.raddr.arready)
+        fsm.If(done).goto_next()
+
+        # state 2
         fsm.If(delay_count > 0)(
             delay_count.dec()
         )
         fsm.If(delay_count == 0).goto_next()
 
-        # state 2
+        # state 3
         rcond = fsm.here
         rdata = self.m.TmpReg(self.datawidth, initval=0,
                               signed=True, prefix='axim_rdata')
@@ -1942,14 +1953,26 @@ def write_delayed(self, fsm, global_addr, value, delay):
         fsm.If(ack).goto_next()
 
         # state 1
+        done = vtypes.Ands(self.waddr.awvalid, self.waddr.awready)
+        fsm.If(done).goto_next()
+
+        # state 2
         fsm.If(delay_count > 0)(
             delay_count.dec()
         )
         fsm.If(delay_count == 0).goto_next()
 
-        # state 2
+        # state 3
         wcond = fsm.here
         wdata = value
         _ = self.write_data(wdata, cond=wcond)
         ack = vtypes.Ors(self.wdata.wready, vtypes.Not(self.wdata.wvalid))
         fsm.If(ack).goto_next()
+
+        # state 4
+        done = vtypes.Ands(self.wdata.wvalid, self.wdata.wready)
+        fsm.If(done).goto_next()
+
+        # state 5
+        res = self.write_completed()
+        fsm.If(res).goto_next()

veriloggen/thread/axis.py

@@ -322,7 +322,10 @@ def _set_register_lite_fsm(self):
                 self.flag[i](0)
             )
 
-        fsm.If(ack).goto_init()
+        fsm.If(ack).goto_next()
+
+        done = vtypes.Ands(self.rdata.rready, self.rdata.rvalid)
+        fsm.If(done).goto_init()
 
         # write
         write_state = fsm.current + 1
@@ -337,7 +340,10 @@ def _set_register_lite_fsm(self):
                 self.register[i](data)
             )
 
-        fsm.If(valid).goto_init()
+        fsm.If(valid).goto_next()
+
+        done = vtypes.Ands(self.wresp.bready, self.wresp.bvalid)
+        fsm.If(done).goto_init()
 
     def read(self, fsm, addr):
         if isinstance(addr, int):