Bug fix of AXI-Lite Master: Changed the outstanding_wcount increment/decrement conditions. Changed the write_acceptable condition. Changed the write_data condition.

Author: shtaxxx

veriloggen/types/axi.py

@@ -1004,12 +1004,12 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
         self.outstanding_wcount = self.m.TmpReg(self.outstanding_wcount_width, initval=0,
                                                 prefix='outstanding_wcount')
 
-        self.seq.If(vtypes.Ands(self.wdata.wvalid, self.wdata.wready),
+        self.seq.If(vtypes.Ands(self.waddr.awvalid, self.waddr.awready),
                     vtypes.Not(vtypes.Ands(self.wresp.bvalid, self.wresp.bready)),
-                    self.outstanding_wcount < (2 ** self.outstanding_wcount_width - 1))(
+                    self.outstanding_wcount < 2 ** self.outstanding_wcount_width - 1)(
             self.outstanding_wcount.inc()
         )
-        self.seq.If(vtypes.Not(vtypes.Ands(self.wdata.wvalid, self.wdata.wready)),
+        self.seq.If(vtypes.Not(vtypes.Ands(self.waddr.awvalid, self.waddr.awready)),
                     vtypes.Ands(self.wresp.bvalid, self.wresp.bready),
                     self.outstanding_wcount > 0)(
             self.outstanding_wcount.dec()
@@ -1043,6 +1043,10 @@ def disable_read(self):
 
         self._read_disabled = True
 
+    def write_acceptable(self):
+        """ AXI-Lite Master must not issue any request until the previous request is completed."""
+        return self.outstanding_wcount == 0
+
     def write_request(self, addr, length=1, cond=None):
         """
         @return ack
@@ -1086,8 +1090,7 @@ def write_data(self, data, cond=None):
         if cond is not None:
             self.seq.If(cond)
 
-        ack = vtypes.Ands(self.write_acceptable(),
-                          vtypes.Ors(self.wdata.wready, vtypes.Not(self.wdata.wvalid)))
+        ack = vtypes.Ors(self.wdata.wready, vtypes.Not(self.wdata.wvalid))
 
         self.seq.If(ack)(
             self.wdata.wdata(data),