led-fsm

Author: shtaxxx

sample/led-fsm/Makefile

@@ -0,0 +1,25 @@
+TARGET=led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: run
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

sample/led-fsm/led.py

@@ -0,0 +1,35 @@
+import sys
+import os
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    fsm = lib.FSM(m, '')
+    fsm_contents = []
+    fsm_contents.append( fsm(count(count + 1), fsm.next()) )
+    fsm_contents.append( fsm(count(count + 2), fsm.next()) )
+    fsm_contents.append( fsm(count(count + 3), fsm.next()) )
+    fsm_contents.append( fsm(If(count < 1024)( fsm.next(0) ).els( fsm.next() )) )
+    fsm_contents.append( fsm(led(led + 1), fsm.next(0)) )
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0),
+            led(0),
+            fsm.next(0)
+        ).els(
+            tuple(fsm_contents)
+        ))
+
+    return m
+
+led = mkLed()
+verilog = led.toVerilog()
+print(verilog)

sample/led-fsm/veriloggen

@@ -0,0 +1 @@
+../../veriloggen

veriloggen/lib.py

@@ -11,7 +11,7 @@ def __init__(self, m, name, width=32):
 
     def next(self, index=None):
         if index is None:
-            return self.state( self.state + 1 )
+            return self.state( len(self) )
         return self.state(index)
 
     def cond(self, name='fsm_label'):