1st pytest of generate statement is passed.

Author: shtaxxx

sample/test/generate/Makefile

@@ -0,0 +1,30 @@
+TARGET=led.py
+TEST=test_led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

sample/test/generate/led.py

@@ -0,0 +1,60 @@
+import sys
+import os
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    num_inst = m.Parameter('NUM_INST', 4)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + 1)
+            )
+        ))
+
+    # genvar i;
+    i = m.Genvar('i')
+    
+    # generate for(i=0; i<NUM_INST; i=i+1) begin: gen_for;
+    gen_for = m.GenerateFor(i(0), i<num_inst, i(i+1), scope='gen_for')
+    gen_count = gen_for.Reg('gen_count', 32)
+    
+    # if(i==0) begin: gen_if_true // generate-if
+    gen_if = gen_for.GenerateIf(i == 0, 'gen_if_true')
+    gen_if.Always(Posedge(clk))(
+        gen_count(count)
+    )
+
+    # end else begin // gen_if_false else
+    gen_if = gen_if.Else('gen_if_false')
+    gen_if_count = gen_if.Reg('gen_if_count', 32)
+    gen_if.Always(Posedge(clk))(
+        gen_count(Scope(gen_for[i-1], gen_count)),
+        gen_if_count(gen_count),
+    )
+    # ... end endgenerate
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(0)
+        ).Else(
+            If(Scope(gen_for[num_inst-1], gen_if, gen_if_count) == 1024 - 1)(
+                led(led + 1)
+            )))
+    
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    verilog = led.to_verilog()
+    print(verilog)

sample/test/generate/test_led.py

@@ -0,0 +1,68 @@
+import led
+
+expected_verilog = """
+module blinkled #
+  ( 
+   parameter WIDTH = 8,
+   parameter NUM_INST = 4
+  )
+  ( 
+   input CLK, 
+   input RST,
+   output reg [WIDTH-1:0] LED
+  );
+
+  reg [32-1:0] count;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end
+  end
+
+  genvar i;
+  generate for(i=0; i<NUM_INST; i=i+1) begin: gen_for
+    reg [32-1:0] gen_count;
+    if(i == 0) begin: gen_if_true
+      always @(posedge CLK) begin
+        gen_count <= count;
+      end
+    end else begin: gen_if_false
+      reg [32-1:0] gen_if_count;
+      always @(posedge CLK) begin
+        gen_count <= gen_for[i-1].gen_count;
+        gen_if_count <= gen_count;
+      end
+    end
+  end endgenerate
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      if(gen_for[NUM_INST-1].gen_if_false.gen_if_count == 1023) begin
+        LED <= LED + 1;
+      end 
+    end
+  end
+endmodule
+"""
+
+def test_led():
+    led_module = led.mkLed()
+    led_code = led_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(led_code == expected_code)

sample/test/generate/veriloggen

@@ -0,0 +1 @@
+../../../veriloggen

veriloggen/__init__.py

@@ -11,7 +11,7 @@
 sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 
 from vtypes import *
-from module import Module, StubModule
+from module import Module, StubModule, Instance, GenerateFor, GenerateIf
 from function import Function, FunctionCall
 from task import Task, TaskCall
 from from_verilog import read_verilog_stubmodule, read_verilog_module