manyled

Author: shtaxxx

sample/manyled/Makefile

@@ -0,0 +1,30 @@
+TARGET=led.py
+TEST=test_led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

sample/manyled/led.py

@@ -0,0 +1,46 @@
+import sys
+import os
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    # function to add an LED port
+    def add_led(m, postfix, limit=1024):
+        led = m.OutputReg('LED'+postfix, width)
+        count = m.Reg('count'+postfix, 32)
+
+        m.Always(Posedge(clk))(
+            If(rst)(
+                count(0)
+            ).Else(
+                If(count == limit - 1)(
+                    count(0)
+                ).Else(
+                    count(count + 1)
+                )
+            ))
+    
+        m.Always(Posedge(clk))(
+            If(rst)(
+                led(0)
+            ).Else(
+                If(count == limit - 1)(
+                    led(led + 1)
+                )
+            ))
+
+    # call 'add_led' to add LED ports
+    for i in range(4):
+        add_led(m, '_' + str(i), limit=i*10 + 10)
+    
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    # led.to_verilog(filename='tmp.v')
+    verilog = led.to_verilog()
+    print(verilog)

sample/manyled/test_led.py

@@ -0,0 +1,114 @@
+import led
+
+expected_verilog = """
+module blinkled #
+  ( 
+   parameter WIDTH = 8
+  )
+  ( 
+   input CLK, 
+   input RST,
+   output reg [WIDTH-1:0] LED_0,
+   output reg [WIDTH-1:0] LED_1,
+   output reg [WIDTH-1:0] LED_2,
+   output reg [WIDTH-1:0] LED_3
+  );
+  reg [32-1:0] count_0;
+  reg [32-1:0] count_1;
+  reg [32-1:0] count_2;
+  reg [32-1:0] count_3;
+  always @(posedge CLK) begin
+    if(RST) begin
+      count_0 <= 0;
+    end else begin
+      if(count_0 == 9) begin
+        count_0 <= 0;
+      end else begin
+        count_0 <= count_0 + 1;
+      end
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED_0 <= 0;
+    end else begin
+      if(count_0 == 9) begin
+        LED_0 <= LED_0 + 1;
+      end 
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      count_1 <= 0;
+    end else begin
+      if(count_1 == 19) begin
+        count_1 <= 0;
+      end else begin
+        count_1 <= count_1 + 1;
+      end
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED_1 <= 0;
+    end else begin
+      if(count_1 == 19) begin
+        LED_1 <= LED_1 + 1;
+      end 
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      count_2 <= 0;
+    end else begin
+      if(count_2 == 29) begin
+        count_2 <= 0;
+      end else begin
+        count_2 <= count_2 + 1;
+      end
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED_2 <= 0;
+    end else begin
+      if(count_2 == 29) begin
+        LED_2 <= LED_2 + 1;
+      end 
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      count_3 <= 0;
+    end else begin
+      if(count_3 == 39) begin
+        count_3 <= 0;
+      end else begin
+        count_3 <= count_3 + 1;
+      end
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED_3 <= 0;
+    end else begin
+      if(count_3 == 39) begin
+        LED_3 <= LED_3 + 1;
+      end 
+    end
+  end
+endmodule
+"""
+
+def test_led():
+    led_module = led.mkLed()
+    led_code = led_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(led_code == expected_code)

sample/manyled/veriloggen

@@ -0,0 +1 @@
+../../veriloggen