Some features such as bit concat, slice, pointer, and integer with width are implemented.

Author: shtaxxx

sample/led-class/veriloggen

@@ -0,0 +1,34 @@
+import sys
+import os
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            count(count + 1)
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(Int(0b00000001, width=8, base=2))
+        ).Else(
+            If(count == 1024 - 1)(
+                led( Cat(led[width-2:0], led[width-1]) )
+            )
+        ))
+
+    return m
+
+led = mkLed()
+verilog = led.to_verilog()
+print(verilog)

sample/led-fsm/veriloggen

@@ -0,0 +1 @@
+../../../veriloggen

sample/led-class/Makefile renamed to sample/test/cat/Makefile

@@ -0,0 +1 @@
+../../../veriloggen

sample/test/cat/led.py

@@ -0,0 +1,25 @@
+TARGET=led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: run
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

sample/test/cat/veriloggen

@@ -29,5 +29,5 @@ def mkLed():
     return m
 
 led = mkLed()
-verilog = led.to_verilog("tmp.v")
+verilog = led.to_verilog()
 print(verilog)