Naming rule is changed

Author: shtaxxx

sample/bram/bram.py

@@ -5,10 +5,13 @@
 from veriloggen import *
 
 class BramInterface(Interface):
-    def __init__(self, m, prefix, postfix, addrwidth, datawidth, direction):
+    def __init__(self, m, prefix='', postfix='', addrwidth=10, datawidth=32, direction='in'):
         Interface.__init__(self, m, prefix, postfix)
 
+        if direction != 'in' and direction != 'out':
+            raise ValueError("direction should be 'in or 'out''")
         self.direction = direction
+        
         self.addrwidth = self.Parameter('ADDR_WIDTH', addrwidth)
         self.datawidth = self.Parameter('DATA_WIDTH', datawidth)
 
@@ -27,7 +30,7 @@ def mkBram(name):
     datawidth = m.Parameter('DATA_WIDTH', 32)
 
     clk = m.Input('CLK')
-    bramif = BramInterface(m, '', '', addrwidth, datawidth, direction='in')
+    bramif = BramInterface(m, addrwidth=addrwidth, datawidth=datawidth, direction='in')
 
     d_addr = m.Reg('d_' + bramif.addr.name, datawidth)
     mem = m.Reg('mem', datawidth, Int(2)**addrwidth)
@@ -47,29 +50,30 @@ def mkTop():
     datawidth = m.Parameter('DATA_WIDTH', 32)
     clk = m.Input('CLK')
     rst = m.Input('RST')
-    bramif = BramInterface(m, 'bram_', '', addrwidth, datawidth, direction='out')
+    bramif = BramInterface(m, prefix='bram_',
+                           addrwidth=addrwidth, datawidth=datawidth, direction='out')
 
     params = collections.OrderedDict()
-    params.update(bramif.connectAllParameters())
+    params.update(bramif.connect_all_parameters())
 
     ports = collections.OrderedDict()
     ports.update(clk.connect())
-    ports.update(bramif.connectAllPorts())
+    ports.update(bramif.connect_all_ports())
 
     m.Instance(bram, 'inst_bram', params, ports)
 
     fsm = lib.FSM(m, 'fsm')
     m.Always(Posedge(clk))(
         If(rst)(
             bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.next(0)
-        ).els(
+        ).Else(
             fsm( bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.next() ),
             fsm( bramif.datain(bramif.datain + 4), fsm.next() ),
             fsm( bramif.write(0), fsm.next() ),
             fsm( 
                 If(bramif.addr == 128)(
                     bramif.addr(0), fsm.next(0)
-                ).els(
+                ).Else(
                     bramif.addr(bramif.addr + 1), fsm.next(1)
                 ))
             ))
@@ -79,5 +83,5 @@ def mkTop():
 #-------------------------------------------------------------------------------
 bram = mkBram('my_')
 top = mkTop()
-verilog = ''.join( (bram.toVerilog(), top.toVerilog()) )
+verilog = ''.join( (bram.to_verilog(), top.to_verilog()) )
 print(verilog)

sample/led-class/led.py

@@ -14,66 +14,20 @@ def __init__(self, name='blinkled'):
         self.Always(Posedge(self.clk))(
             If(self.rst)(
                 self.count(0)
-            ).els(
+            ).Else(
                 self.count(self.count + 1)
             ))
 
         self.Always(Posedge(self.clk))(
             If(self.rst)(
                 self.led(0)
-            ).els(
+            ).Else(
                 If(self.count == 1024 - 1)(
                     self.led(self.led + 1)
                 )
             ))
 
 #-------------------------------------------------------------------------------
 led = Led()
-verilog = led.toVerilog()
+verilog = led.to_verilog()
 print(verilog)
-
-#-------------------------------------------------------------------------------
-expected_verilog = """
-module blinkled #
-  ( 
-   parameter WIDTH = 8
-  )
-  ( 
-   input CLK, 
-   input RST,
-   output reg [WIDTH-1:0] LED
-  );
-  reg [32-1:0] count;
-
-  always @(posedge CLK) begin
-    if(RST) begin
-      count <= 0;
-    end else begin
-      count <= count + 1;
-    end
-  end
-  always @(posedge CLK) begin
-    if(RST) begin
-      LED <= 0;
-    end else begin
-      if(count == 1023) begin
-        LED <= LED + 1;
-      end 
-    end
-  end
-endmodule
-"""
-
-#from pyverilog.vparser.parser import VerilogParser
-#from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
-#parser = VerilogParser()
-#expected_verilog_ast = parser.parse(expected_verilog)
-#codegen = ASTCodeGenerator()
-#expected_verilog_code = codegen.visit(expected_verilog_ast)
-
-#print('// Sample Verilog code -> AST -> Verilog code')
-#print(expected_verilog_code)
-
-#import difflib
-#diff = difflib.unified_diff(verilog.splitlines(), expected_verilog_code.splitlines())
-#print('\n'.join(list(diff)))

sample/led-fsm/led.py

@@ -18,16 +18,16 @@ def mkLed():
             count(0),
             led(0),
             fsm.next(0)
-        ).els(
+        ).Else(
             fsm(count(count + 1), fsm.next()),
             fsm(count(count + 2), fsm.next()),
             fsm(count(count + 3), fsm.next()),
-            fsm(If(count < 1024)( fsm.next(0) ).els( fsm.next() )),
+            fsm(If(count < 1024)( fsm.next(0) ).Else( fsm.next() )),
             fsm(led(led + 1), fsm.next(0))
         ))
 
     return m
 
 led = mkLed()
-verilog = led.toVerilog()
+verilog = led.to_verilog("tmp.v")
 print(verilog)

sample/led/Makefile

@@ -22,4 +22,4 @@ check:
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py *.out
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v

sample/led/led.py

@@ -13,14 +13,14 @@ def mkLed():
     m.Always(Posedge(clk))(
         If(rst)(
             count(0)
-        ).els(
+        ).Else(
             count(count + 1)
         ))
 
     m.Always(Posedge(clk))(
         If(rst)(
             led(0)
-        ).els(
+        ).Else(
             If(count == 1024 - 1)(
                 led(led + 1)
             )
@@ -30,7 +30,8 @@ def mkLed():
 
 #-------------------------------------------------------------------------------
 led = mkLed()
-verilog = led.toVerilog()
+## if filename is not None: the generated source code is written to the file.
+verilog = led.to_verilog(filename='tmp.v')
 print(verilog)
 
 #-------------------------------------------------------------------------------
@@ -65,16 +66,13 @@ def mkLed():
 endmodule
 """
 
-#from pyverilog.vparser.parser import VerilogParser
-#from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
-#parser = VerilogParser()
-#expected_verilog_ast = parser.parse(expected_verilog)
-#codegen = ASTCodeGenerator()
-#expected_verilog_code = codegen.visit(expected_verilog_ast)
+from pyverilog.vparser.parser import VerilogParser
+from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+parser = VerilogParser()
+expected_verilog_ast = parser.parse(expected_verilog)
+codegen = ASTCodeGenerator()
+expected_verilog_code = codegen.visit(expected_verilog_ast)
 
-#print('// Sample Verilog code -> AST -> Verilog code')
-#print(expected_verilog_code)
-
-#import difflib
-#diff = difflib.unified_diff(verilog.splitlines(), expected_verilog_code.splitlines())
-#print('\n'.join(list(diff)))
+import difflib
+diff = difflib.unified_diff(verilog.splitlines(), expected_verilog_code.splitlines())
+print('\n'.join(list(diff)))

veriloggen/Makefile

@@ -1,14 +1,4 @@
-PYTHON = python3
-#OPT=-m pdb
-
-VERILOGGEN=veriloggen.py
-#SRCS=
-
 .PHONY: clean
 clean:
 	make clean -C utils
 	rm -rf *.pyc __pycache__ parsetab.py *.out *.html
-
-.PHONY: run
-run:
-	$(PYTHON) $(OPT) $(VERILOGGEN) $(SRCS)

veriloggen/__init__.py

@@ -1,8 +1,22 @@
-import sys
+#-------------------------------------------------------------------------------
+# veriloggen.py
+#
+# Veriloggen: A library for constructing a Verilog HDL source code in Python
+# 
+# Copyright (C) 2015, Shinya Takamaeda-Yamazaki
+# License: Apache 2.0
+#-------------------------------------------------------------------------------
+
 import os
-if sys.version_info[0] < 3:
-    import utils
-    from veriloggen import *
-else:
-    sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
-    from veriloggen.veriloggen import *
+import sys
+
+sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
+
+import utils.version
+import vtypes
+
+from module import Module
+from interface import Interface
+from vtypes import *
+
+import lib

veriloggen/interface.py

@@ -13,13 +13,14 @@ def __init__(self, module, prefix='', postfix=''):
         self.prefix = prefix
         self.postfix = postfix
 
+    #---------------------------------------------------------------------------
     def get_name(self, name):
         return self.prefix + name + self.postfix
 
     def get_basename(self, name):
         return re.sub(r'' + self.postfix + '$', '', name.replace(self.prefix, '', 1))
 
-    
+    #---------------------------------------------------------------------------
     def Input(self, name, width=1, length=None, signed=False, value=None):
         new_name = self.get_name(name)
         return self.module.Input(name, width, length, signed, value)
@@ -52,7 +53,8 @@ def Localparam(self, name, value, width=None, signed=False):
         new_name = self.get_name(name)
         return self.module.Localparam(name, value, width, signed)
 
-    def connectAllPorts(self, prefix='', postfix=''):
+    #---------------------------------------------------------------------------
+    def connect_all_ports(self, prefix='', postfix=''):
         inputs = [ s for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Input) ]
         outputs = [ s for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Output) ]
         inouts = [ s for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Inout) ]
@@ -76,7 +78,8 @@ def connectAllPorts(self, prefix='', postfix=''):
             ret[name] = getattr(self, p)
         return ret
 
-    def connectAllParameters(self, prefix='', postfix=''):
+    #---------------------------------------------------------------------------
+    def connect_all_parameters(self, prefix='', postfix=''):
         parameters = [ s for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Parameter) ]
         localparams = [ s for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Localparam) ]
         ret = collections.OrderedDict()
@@ -88,13 +91,13 @@ def connectAllParameters(self, prefix='', postfix=''):
             ret[name] = getattr(self, p)
         return ret
 
-    def getPorts(self):
+    def get_ports(self):
         return ([ getattr(self, s) for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Input) ] +
                 [ getattr(self, s) for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Output) ] +
                 [ getattr(self, s) for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Inout) ] +
                 [ getattr(self, s) for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Reg) ] +
                 [ getattr(self, s) for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Wire) ])
 
-    def getParameters(self):
+    def get_parameters(self):
         return ([ getattr(self, s) for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Parameter) ] +
                 [ getattr(self, s) for s in self.__dir__() if isinstance(getattr(self, s), vtypes.Localparam) ])

veriloggen/module.py

@@ -5,12 +5,12 @@
 sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 
 import vtypes
-import toverilog
+import to_verilog
 
 class Module(object):
     """ Verilog Module class """
-    def __init__(self, name):
-        self.name = name
+    def __init__(self, name=None):
+        self.name = name if name is not None else self.__class__.__name__
         self.variable = collections.OrderedDict()
         self.io_variable = collections.OrderedDict()
         self.constant = collections.OrderedDict()
@@ -79,31 +79,30 @@ def Instance(self, module, instname, params, ports):
         return t
 
     #---------------------------------------------------------------------------
-    def isReg(self, name):
+    def is_reg(self, name):
         if name not in self.variable: return False
         if isinstance(self.variable[name], vtypes.Reg): return True
         return False
 
-    def isWire(self, name):
+    def is_wire(self, name):
         if name not in self.variable and name not in self.io_variable: return False
         if name in self.variable and isinstance(self.variable[name], vtypes.Wire): return True
         if name in self.variable and isinstance(self.variable[name], vtypes.Reg): return False
         if name in self.io_variable: return True
         return False
 
-    def isOutput(self, name):
+    def is_output(self, name):
         if name not in self.io_variable: return False
         if isinstance(self.io_variable[name], vtypes.Output): return True
         return False
 
     #---------------------------------------------------------------------------
-    def getIO(self):
+    def get_io(self):
         return self.io_variable
 
-    def getIOname(self):
+    def get_io_name(self):
         return tuple(self.io_variable.keys())
 
     #---------------------------------------------------------------------------
-    def toVerilog(self):
-        return toverilog.toVerilog(self)
-
+    def to_verilog(self, filename=None):
+        return to_verilog.to_verilog(self, filename)