pipeline test

Author: shtaxxx

sample/test/pipeline/Makefile

@@ -0,0 +1,30 @@
+TARGET=led.py
+TEST=test_led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

sample/test/pipeline/led.py

@@ -0,0 +1,25 @@
+import sys
+import os
+from veriloggen import *
+
+def mkLed(pipe=True):
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.Output('LED', width)
+    
+    value = m.Reg('value', width) if pipe else m.Wire('value', width)
+    next_value = value(10)
+
+    if pipe: m.Always(Posedge(clk))( next_value )         
+    else: m.Assign( next_value )
+    
+    m.Assign(led(value))
+    return m
+
+if __name__ == '__main__':
+    led = mkLed(True)
+    # led.to_verilog(filename='tmp.v')
+    verilog = led.to_verilog()
+    print(verilog)

sample/test/pipeline/test_led.py

@@ -0,0 +1,32 @@
+import led
+
+expected_verilog = """
+module blinkled #
+  ( 
+   parameter WIDTH = 8
+  )
+  ( 
+   input CLK, 
+   input RST,
+   output [WIDTH-1:0] LED
+  );
+  reg [WIDTH-1:0] value;
+  always @(posedge CLK) begin
+    value <= 10;
+  end
+  assign LED = value;
+endmodule
+"""
+
+def test_led():
+    led_module = led.mkLed()
+    led_code = led_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == led_code)

sample/test/pipeline/veriloggen

@@ -0,0 +1 @@
+../../../veriloggen