read_verilog is updated: directory name and assertion order

Author: shtaxxx

sample/test/read_verilog/module/test_led.py

@@ -66,4 +66,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(top_code == expected_code)
+    assert(expected_code == top_code)

sample/test/read_verilog/module-generate/Makefile renamed to sample/test/read_verilog/module_generate/Makefile

@@ -86,4 +86,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(top_code == expected_code)
+    assert(expected_code == top_code)

sample/test/read_verilog/module-generate/led.py renamed to sample/test/read_verilog/module_generate/led.py

@@ -34,4 +34,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(top_code == expected_code)
+    assert(expected_code == top_code)