Updated test cases

Author: shtaxxx

tests/extension/types_/axi_/memory_model_read/types_memory_model_read.py

@@ -86,7 +86,8 @@ def mkTest(memimg_name=None):
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    # simulation.setup_waveform(m, uut, m.get_vars())
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/extension/types_/axi_/memory_model_write/types_memory_model_write.py

@@ -118,7 +118,8 @@ def mkTest(memimg_name=None):
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    # simulation.setup_waveform(m, uut, m.get_vars())
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/extension/types_/axi_/read/types_axi_read.py

@@ -122,25 +122,22 @@ def mkTest():
 
     ack = Ors(ports['myaxi_rready'], Not(ports['myaxi_rvalid']))
 
-    raddr_fsm.If(Ands(ack, Not(ports['myaxi_rlast'])))(
+    raddr_fsm.If(ack)(
         ports['myaxi_rdata'].inc(),
         ports['myaxi_rvalid'](1),
         ports['myaxi_rlast'](0),
         _arlen.dec()
     )
-    raddr_fsm.Then().If(_arlen == 0)(
+    raddr_fsm.If(ack, _arlen == 0)(
         ports['myaxi_rlast'](1),
     )
-    raddr_fsm.Delay(1)(
+    raddr_fsm.If(ack, _arlen == 0).goto_next()
+
+    raddr_fsm.If(ports['myaxi_rready'])(
         ports['myaxi_rvalid'](0),
         ports['myaxi_rlast'](0)
     )
-    raddr_fsm.If(Ands(ports['myaxi_rvalid'], Not(ports['myaxi_rready'])))(
-        ports['myaxi_rvalid'](ports['myaxi_rvalid']),
-        ports['myaxi_rlast'](ports['myaxi_rlast']),
-    )
-    raddr_fsm.If(Ands(ports['myaxi_rvalid'], ports[
-                 'myaxi_rready'], ports['myaxi_rlast'])).goto_next()
+    raddr_fsm.If(ports['myaxi_rready']).goto_next()
 
     raddr_fsm.goto_next()
 
@@ -152,7 +149,8 @@ def mkTest():
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    # simulation.setup_waveform(m, uut, m.get_vars())
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/extension/types_/axi_/read_lite/types_axi_read_lite.py

@@ -114,19 +114,16 @@ def mkTest(memimg_name=None):
     )
     raddr_fsm.goto_next()
 
-    ack = Ors(ports['myaxi_rready'], Not(ports['myaxi_rvalid']))
-
-    raddr_fsm.If(ack)(
+    raddr_fsm(
         ports['myaxi_rdata'].inc(),
         ports['myaxi_rvalid'](1),
     )
-    raddr_fsm.Delay(1)(
-        ports['myaxi_rvalid'](0),
-    )
-    raddr_fsm.If(Ands(ports['myaxi_rvalid'], Not(ports['myaxi_rready'])))(
-        ports['myaxi_rvalid'](ports['myaxi_rvalid']),
+    raddr_fsm.goto_next()
+
+    raddr_fsm.If(ports['myaxi_rready'])(
+        ports['myaxi_rvalid'](0)
     )
-    raddr_fsm.If(Ands(ports['myaxi_rvalid'], ports['myaxi_rready'])).goto_next()
+    raddr_fsm.If(ports['myaxi_rready']).goto_next()
 
     raddr_fsm.goto_next()
 
@@ -138,7 +135,8 @@ def mkTest(memimg_name=None):
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    # simulation.setup_waveform(m, uut, m.get_vars())
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/extension/types_/axi_/slave_read/types_axi_slave_read.py

@@ -111,7 +111,8 @@ def mkTest():
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    # simulation.setup_waveform(m, uut, m.get_vars())
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/extension/types_/axi_/slave_read_lite/types_axi_slave_read_lite.py

@@ -104,7 +104,8 @@ def mkTest():
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    # simulation.setup_waveform(m, uut, m.get_vars())
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/extension/types_/axi_/slave_readwrite/types_axi_slave_readwrite.py

@@ -159,7 +159,8 @@ def mkTest():
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    # simulation.setup_waveform(m, uut, m.get_vars())
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/extension/types_/axi_/slave_readwrite_lite/types_axi_slave_readwrite_lite.py

@@ -139,7 +139,8 @@ def mkTest():
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    # simulation.setup_waveform(m, uut, m.get_vars())
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/extension/types_/axi_/slave_readwrite_simultaneous/types_axi_slave_readwrite_simultaneous.py

@@ -169,7 +169,8 @@ def mkTest():
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    # simulation.setup_waveform(m, uut, m.get_vars())
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/extension/types_/axi_/slave_write/types_axi_slave_write.py

@@ -97,6 +97,8 @@ def mkTest():
     fsm.If(Not(_axi.wdata.wvalid)).goto_next()
 
     # verify
+    fsm.If(_axi.write_completed()).goto_next()
+
     expected_sum = (((0 + awlen1 - 1) * awlen1) // 2 +
                     ((0 + awlen2 - 1) * awlen2) // 2)
     fsm(
@@ -113,7 +115,8 @@ def mkTest():
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    # simulation.setup_waveform(m, uut, m.get_vars())
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)