Assigned initvals to TmpRegLike signals

Author: shtaxxx

veriloggen/types/axi.py

@@ -500,22 +500,26 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
             self.wuser.assign(user_mode)
 
         # user-side signals before skidbuffer
-        wdata = m.TmpRegLike(self.wdata, prefix='_'.join(['', name, 'wdata', 'sb']))
-        wstrb = m.TmpRegLike(self.wstrb, prefix='_'.join(['', name, 'wstrb', 'sb']))
-        wlast = m.TmpRegLike(self.wlast, prefix='_'.join(['', name, 'wlast', 'sb']))
-        wvalid = m.TmpRegLike(self.wvalid, prefix='_'.join(['', name, 'wvalid', 'sb']))
+        wdata = m.TmpRegLike(self.wdata, initval=0,
+                             prefix='_'.join(['', name, 'wdata', 'sb']))
+        wstrb = m.TmpRegLike(self.wstrb, initval=0,
+                             prefix='_'.join(['', name, 'wstrb', 'sb']))
+        wlast = m.TmpRegLike(self.wlast, initval=0,
+                             prefix='_'.join(['', name, 'wlast', 'sb']))
+        wvalid = m.TmpRegLike(self.wvalid, initval=0,
+                              prefix='_'.join(['', name, 'wvalid', 'sb']))
         wready = m.TmpWireLike(self.wready, prefix='_'.join(['', name, 'wready', 'sb']))
 
         # skidbuffer
         sb = SkidBuffer(m, clk, rst,
-                        wvalid, self.wready, *[wdata, wstrb, wlast],
+                        wvalid, self.wready, *[wlast, wstrb, wdata],
                         prefix='_'.join(['', 'sb', name, 'writedata']))
         wready.assign(sb.ready)
 
         # AXI-side signals after skidbuffer
-        self.wdata.assign(sb[0])
+        self.wdata.assign(sb[2])
         self.wstrb.assign(sb[1])
-        self.wlast.assign(sb[2])
+        self.wlast.assign(sb[0])
         self.wvalid.assign(sb.valid)
 
         # save AXI-side references
@@ -751,10 +755,10 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
 
         # skidbuffer
         sb = SkidBuffer(m, clk, rst,
-                        self.rvalid, rready, *[self.rdata, self.rlast],
+                        self.rvalid, rready, *[self.rlast, self.rdata],
                         prefix='_'.join(['', 'sb', name, 'readdata']))
-        rdata.assign(sb[0])
-        rlast.assign(sb[1])
+        rdata.assign(sb[1])
+        rlast.assign(sb[0])
         rvalid.assign(sb.valid)
 
         # AXI-side signals after skidbuffer
@@ -897,20 +901,23 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
         self.seq = Seq(m, name + '_wdata', clk, rst)
 
         # user-side signals before skidbuffer
-        wdata = m.TmpRegLike(self.wdata, prefix='_'.join(['', name, 'wdata', 'sb']))
-        wstrb = m.TmpRegLike(self.wstrb, prefix='_'.join(['', name, 'wstrb', 'sb']))
-        wvalid = m.TmpRegLike(self.wvalid, prefix='_'.join(['', name, 'wvalid', 'sb']))
+        wdata = m.TmpRegLike(self.wdata, initval=0,
+                             prefix='_'.join(['', name, 'wdata', 'sb']))
+        wstrb = m.TmpRegLike(self.wstrb, initval=0,
+                             prefix='_'.join(['', name, 'wstrb', 'sb']))
+        wvalid = m.TmpRegLike(self.wvalid, initval=0,
+                              prefix='_'.join(['', name, 'wvalid', 'sb']))
         wready = m.TmpWireLike(self.wready, prefix='_'.join(['', name, 'wready', 'sb']))
 
         # skidbuffer
         sb = SkidBuffer(m, clk, rst,
-                        wvalid, self.wready, *[wdata, wstrb],
+                        wvalid, self.wready, *[wstrb, wdata],
                         prefix='_'.join(['', 'sb', name, 'writedata']))
         wready.assign(sb.ready)
 
         # AXI-side signals after skidbuffer
-        self.wdata.assign(sb[0])
-        self.wstrb.assign(sb[1])
+        self.wdata.assign(sb[1])
+        self.wstrb.assign(sb[0])
         self.wvalid.assign(sb.valid)
 
         # save AXI-side references

veriloggen/types/skidbuffer.py

@@ -24,23 +24,32 @@ def __init__(self, m, clk, rst,
         self.m_ready = m_ready
 
         width = 0
+        _s_values = []
         for s_value in s_values:
+            v = m.TmpWireLike(s_value, prefix=prefix + '_s_value')
+            v.assign(s_value)
+            _s_values.append(v)
             w = s_value.get_width()
             if w is None:
                 w = 1
             width += w
 
-        s_data = m.TmpWire(width, prefix=prefix + '_data')
-        s_data.assign(vtypes.Cat(*s_values))
+        _s_data = m.TmpWire(width, prefix=prefix + '_s_data')
+        _s_data.assign(vtypes.Cat(*_s_values))
+
+        _s_valid = m.TmpWire(prefix=prefix + '_s_valid')
+        _s_valid.assign(s_valid)
+        _m_ready = m.TmpWire(prefix=prefix + '_m_ready')
+        _m_ready.assign(m_ready)
 
         (m_data, m_valid, s_ready) = make_skidbuffer(m, clk, rst,
-                                                     s_data, s_valid, m_ready,
+                                                     _s_data, _s_valid, _m_ready,
                                                      prefix=prefix)
 
         self.m_values = []
         msb = width - 1
         for s_value in s_values:
-            v = m.TmpWireLike(s_value, prefix=prefix + '_value')
+            v = m.TmpWireLike(s_value, prefix=prefix + '_m_value')
             w = v.get_width()
             if w is None:
                 w = 1
@@ -78,12 +87,12 @@ def make_skidbuffer(m, clk, rst,
         else:
             prefix = 'skidbuffer'
 
-    m_data = m.TmpRegLike(s_data, prefix=prefix + '_data')
+    m_data = m.TmpRegLike(s_data, prefix=prefix + '_data', initval=0)
     m_valid = m.TmpReg(prefix=prefix + '_valid', initval=0)
 
     s_ready = m.TmpWire(prefix=prefix + '_ready')
 
-    tmp_data = m.TmpRegLike(s_data, prefix=prefix + '_tmp_data')
+    tmp_data = m.TmpRegLike(s_data, prefix=prefix + '_tmp_data', initval=0)
     tmp_valid = m.TmpReg(prefix=prefix + '_tmp_valid', initval=0)
 
     next_data = m.TmpWireLike(s_data, prefix=prefix + '_next_data')