visit_Identifier() returns a Reg/Wire objectif both an input/output variable and a reg/wire are found for a specific name.

Author: shtaxxx

veriloggen/verilog/from_verilog.py

@@ -183,6 +183,8 @@ def visit_Identifier(self, node):
         ret = self.m.find_identifier(node.name)
         if ret is None:
             return vtypes.AnyType(name=node.name)
+        if ret.name in self.m.variable:
+            return self.m.variable[ret.name]
         return ret
 
     def visit_IntConst(self, node):