lib_fsm_ test is updated

shtaxxx · shtaxxx · commit 26613aba366d · 2015-10-30T12:06:23.000+09:00
diff --git a/tests/lib_fsm_/branch/lib_fsm_branch.py b/tests/lib_fsm_/branch/lib_fsm_branch.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 class SeqIfElse(object):
diff --git a/tests/lib_fsm_/branch/test_lib_fsm_branch.py b/tests/lib_fsm_/branch/test_lib_fsm_branch.py
@@ -1,4 +1,4 @@
-import led
+import lib_fsm_branch
 
 expected_verilog = """
 module blinkled #
@@ -62,9 +62,9 @@
 endmodule
 """
 
-def test_led():
-    led_module = led.mkLed()
-    led_code = led_module.to_verilog()
+def test():
+    test_module = lib_fsm_branch.mkLed()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -73,4 +73,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == led_code)
+    assert(expected_code == code)
diff --git a/tests/lib_fsm_/delayed/lib_fsm_delayed.py b/tests/lib_fsm_/delayed/lib_fsm_delayed.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_fsm_/delayed/test_lib_fsm_delayed.py b/tests/lib_fsm_/delayed/test_lib_fsm_delayed.py
@@ -1,4 +1,4 @@
-import led
+import lib_fsm_delayed
 
 expected_verilog = """
 module test;
@@ -125,8 +125,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_fsm_delayed.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_fsm_/delayed_cond/lib_fsm_delayed_cond.py b/tests/lib_fsm_/delayed_cond/lib_fsm_delayed_cond.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_fsm_/delayed_cond/test_lib_fsm_delayed_cond.py b/tests/lib_fsm_/delayed_cond/test_lib_fsm_delayed_cond.py
@@ -1,4 +1,4 @@
-import led
+import lib_fsm_delayed_cond
 
 expected_verilog = """
 module test;
@@ -624,8 +624,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_fsm_delayed_cond.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_fsm_/delayed_eager_val/lib_fsm_delayed_eager_val.py b/tests/lib_fsm_/delayed_eager_val/lib_fsm_delayed_eager_val.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_fsm_/delayed_eager_val/test_lib_fsm_delayed_eager_val.py b/tests/lib_fsm_/delayed_eager_val/test_lib_fsm_delayed_eager_val.py
@@ -1,4 +1,4 @@
-import led
+import lib_fsm_delayed_eager_val
 
 expected_verilog = """
 module test;
@@ -889,8 +889,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_fsm_delayed_eager_val.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_fsm_/delayed_eager_val_lazy_cond/lib_fsm_delayed_eager_val_lazy_cond.py b/tests/lib_fsm_/delayed_eager_val_lazy_cond/lib_fsm_delayed_eager_val_lazy_cond.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_fsm_/delayed_eager_val_lazy_cond/test_lib_fsm_delayed_eager_val_lazy_cond.py b/tests/lib_fsm_/delayed_eager_val_lazy_cond/test_lib_fsm_delayed_eager_val_lazy_cond.py
@@ -1,4 +1,4 @@
-import led
+import lib_fsm_delayed_eager_val_lazy_cond
 
 expected_verilog = """
 module test;
@@ -627,8 +627,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_fsm_delayed_eager_val_lazy_cond.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_fsm_/delayed_lazy_cond/lib_fsm_delayed_lazy_cond.py b/tests/lib_fsm_/delayed_lazy_cond/lib_fsm_delayed_lazy_cond.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_fsm_/delayed_lazy_cond/test_lib_fsm_delayed_lazy_cond.py b/tests/lib_fsm_/delayed_lazy_cond/test_lib_fsm_delayed_lazy_cond.py
@@ -1,4 +1,4 @@
-import led
+import lib_fsm_delayed_lazy_cond
 
 expected_verilog = """
 module test;
@@ -374,8 +374,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_fsm_delayed_lazy_cond.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_fsm_/make_case/lib_fsm_make_case.py b/tests/lib_fsm_/make_case/lib_fsm_make_case.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_fsm_/make_case/test_lib_fsm_make_case.py b/tests/lib_fsm_/make_case/test_lib_fsm_make_case.py
@@ -1,4 +1,4 @@
-import led
+import lib_fsm_make_case
 
 expected_verilog = """
 module blinkled #
@@ -53,9 +53,9 @@
 endmodule
 """
 
-def test_led():
-    led_module = led.mkLed()
-    led_code = led_module.to_verilog()
+def test():
+    test_module = lib_fsm_make_case.mkLed()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -64,4 +64,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == led_code)
+    assert(expected_code == code)
diff --git a/tests/lib_fsm_/make_if/lib_fsm_make_if.py b/tests/lib_fsm_/make_if/lib_fsm_make_if.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_fsm_/make_if/test_lib_fsm_make_if.py b/tests/lib_fsm_/make_if/test_lib_fsm_make_if.py
@@ -1,4 +1,4 @@
-import led
+import lib_fsm_make_if
 
 expected_verilog = """
 module blinkled #
@@ -51,9 +51,9 @@
 endmodule
 """
 
-def test_led():
-    led_module = led.mkLed()
-    led_code = led_module.to_verilog()
+def test():
+    test_module = lib_fsm_make_if.mkLed()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -62,4 +62,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == led_code)
+    assert(expected_code == code)
diff --git a/tests/lib_fsm_/multiple/lib_fsm_multiple.py b/tests/lib_fsm_/multiple/lib_fsm_multiple.py
@@ -1,5 +1,9 @@
 import sys
 import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_fsm_/multiple/test_lib_fsm_multiple.py b/tests/lib_fsm_/multiple/test_lib_fsm_multiple.py
@@ -1,4 +1,4 @@
-import led
+import lib_fsm_multiple
 
 expected_verilog = """
 module blinkled #
@@ -58,9 +58,9 @@
 endmodule
 """
 
-def test_led():
-    led_module = led.mkLed()
-    led_code = led_module.to_verilog()
+def test():
+    test_module = lib_fsm_multiple.mkLed()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -69,4 +69,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == led_code)
+    assert(expected_code == code)
diff --git a/tests/lib_fsm_/prev/lib_fsm_prev.py b/tests/lib_fsm_/prev/lib_fsm_prev.py
@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
diff --git a/tests/lib_fsm_/prev/test_lib_fsm_prev.py b/tests/lib_fsm_/prev/test_lib_fsm_prev.py
@@ -1,4 +1,4 @@
-import led
+import lib_fsm_prev
 
 expected_verilog = """
 module test;
@@ -136,8 +136,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = lib_fsm_prev.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
