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instance_ is updated
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4 files changed

+14
-8
lines changed

4 files changed

+14
-8
lines changed

tests/instance_/named_args/named_args.py

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import os
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import collections
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
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from veriloggen import *
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def mkLed():

tests/instance_/named_args/test_named_args.py

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import led
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import named_args
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expected_verilog = """
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module top #
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"""
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def test_led():
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top_module = led.mkTop()
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top_code = top_module.to_verilog()
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test_module = named_args.mkTop()
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code = test_module.to_verilog()
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from pyverilog.vparser.parser import VerilogParser
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -66,4 +66,4 @@ def test_led():
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codegen = ASTCodeGenerator()
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expected_code = codegen.visit(expected_ast)
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assert(expected_code == top_code)
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assert(expected_code == code)

tests/instance_/noname_args/noname_args.py

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Original file line numberDiff line numberDiff line change
@@ -2,6 +2,9 @@
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import os
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import collections
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
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from veriloggen import *
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def mkLed():

tests/instance_/noname_args/test_noname_args.py

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@@ -1,4 +1,4 @@
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import led
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import noname_args
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expected_verilog = """
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module top #
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"""
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def test_led():
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top_module = led.mkTop()
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top_code = top_module.to_verilog()
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test_module = noname_args.mkTop()
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code = test_module.to_verilog()
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from pyverilog.vparser.parser import VerilogParser
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -66,4 +66,4 @@ def test_led():
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codegen = ASTCodeGenerator()
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expected_code = codegen.visit(expected_ast)
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assert(expected_code == top_code)
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assert(expected_code == code)

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