Merge branch 'fix_simulation_outputfile' into develop

Author: shtaxxx

tests/simulation/simulator/verilator/simulation_simulator_verilator.py

@@ -30,7 +30,7 @@ def mkLed():
         led.inc()
     )
 
-    seq.If(led < 4)(
+    seq(
         Systask('display', "LED:%d count:%d", led, count)
     )
 
@@ -50,7 +50,8 @@ def mkTest():
     # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
     # simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
-    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+    # for avaoiding clock/reset timing conflict
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100 + 1)
 
     init.add(
         Delay(1000 * 100),
@@ -64,7 +65,7 @@ def mkTest():
     test = mkTest()
 
     sim = simulation.Simulator(test, sim='verilator')
-    rslt = sim.run(sim_time=10000)
+    rslt = sim.run(sim_time=1000)
     print(rslt)
 
     # sim.view_waveform()

tests/simulation/simulator/verilator/test_simulation_simulator_verilator.py

@@ -15,6 +15,7 @@
 LED:  0 count:         7
 LED:  0 count:         8
 LED:  0 count:         9
+LED:  0 count:        10
 LED:  0 count:         0
 LED:  0 count:         1
 LED:  0 count:         2
@@ -95,60 +96,12 @@
 LED:  2 count:        13
 LED:  2 count:        14
 LED:  2 count:        15
-LED:  2 count:        16
-LED:  2 count:        17
-LED:  2 count:        18
-LED:  2 count:        19
-LED:  2 count:        20
-LED:  2 count:        21
-LED:  2 count:        22
-LED:  2 count:        23
-LED:  2 count:        24
-LED:  2 count:        25
-LED:  2 count:        26
-LED:  2 count:        27
-LED:  2 count:        28
-LED:  2 count:        29
-LED:  2 count:        30
-LED:  2 count:        31
-LED:  3 count:         0
-LED:  3 count:         1
-LED:  3 count:         2
-LED:  3 count:         3
-LED:  3 count:         4
-LED:  3 count:         5
-LED:  3 count:         6
-LED:  3 count:         7
-LED:  3 count:         8
-LED:  3 count:         9
-LED:  3 count:        10
-LED:  3 count:        11
-LED:  3 count:        12
-LED:  3 count:        13
-LED:  3 count:        14
-LED:  3 count:        15
-LED:  3 count:        16
-LED:  3 count:        17
-LED:  3 count:        18
-LED:  3 count:        19
-LED:  3 count:        20
-LED:  3 count:        21
-LED:  3 count:        22
-LED:  3 count:        23
-LED:  3 count:        24
-LED:  3 count:        25
-LED:  3 count:        26
-LED:  3 count:        27
-LED:  3 count:        28
-LED:  3 count:        29
-LED:  3 count:        30
-LED:  3 count:        31
 """
 
 
 def test():
     vg.reset()
     test_module = simulation_simulator_verilator.mkTest()
     sim = vg.simulation.Simulator(test_module, sim='verilator')
-    rslt = sim.run(sim_time=10000)
+    rslt = sim.run(sim_time=1000)
     assert(expected_rslt == rslt)