lib.pipeline is updated: Accumulator is supported.

Author: shtaxxx

sample/tests/lib_pipeline/average/Makefile renamed to sample/tests/lib_pipeline/acc_add/Makefile

@@ -0,0 +1,92 @@
+import sys
+import os
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    x = m.Input('x', 32)
+    y = m.Output('y', 32)
+    prst = m.Input('prst')
+    
+    pipe = lib.Pipeline(m, 'pipe')
+    
+    px = pipe.input(x)
+    psum = pipe.acc_add(px, initval=0, resetcond=prst)
+    psum.output(y)
+    
+    pipe.make_always(clk, rst)
+
+    return m
+
+def mkTest(numports=8):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+    
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+    x = ports['x']
+    y = ports['y']
+    prst = ports['prst']
+    
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    reset_done = m.Reg('reset_done', initval=0)
+    
+    reset_stmt = []
+    reset_stmt.append( reset_done(0) )
+    reset_stmt.append( prst(0) )
+    reset_stmt.append( x(0) )
+    
+    lib.simulation.setup_waveform(m, uut)
+    lib.simulation.setup_clock(m, clk, hperiod=5)
+    init = lib.simulation.setup_reset(m, rst, reset_stmt, period=100)
+
+    nclk = lib.simulation.next_clock
+    
+    init.add(
+        Delay(1000),
+        reset_done(1),
+        nclk(clk),
+        Delay(10000),
+        Systask('finish'),
+    )
+
+    x_count = m.TmpReg(32, initval=0)
+
+    xfsm = lib.FSM(m, 'xfsm')
+    xfsm.goto_next(cond=reset_done)
+    xfsm.add(x.inc())
+    xfsm.add(x_count.inc())
+    xfsm.goto_next(cond=x_count==10)
+    xfsm.add(x(0))
+    for i in range(5):
+        xfsm.goto_next()
+    xfsm.add(Systask('finish'))
+    
+    xfsm.make_always(clk, rst)
+    
+    
+    m.Always(Posedge(clk))(
+        If(reset_done)(
+            Systask('display', 'x=%d', x),
+            Systask('display', 'y=%d', y)
+        )
+    )
+
+    return m
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)

sample/tests/lib_pipeline/acc_add/led.py

@@ -0,0 +1,156 @@
+import led
+
+expected_verilog = """
+module test;
+  reg CLK;
+  reg RST;
+  reg [32-1:0] x;
+  wire [32-1:0] y;
+  reg prst;
+
+  blinkled
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .x(x),
+    .y(y),
+    .prst(prst)
+  );
+
+  reg reset_done;
+
+  initial begin
+    $dumpfile("uut.vcd");
+    $dumpvars(0, uut);
+  end
+
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = (!CLK);
+    end
+  end
+
+
+  initial begin
+    RST = 0;
+    reset_done = 0;
+    prst = 0;
+    x = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #1000;
+    reset_done = 1;
+    @(posedge CLK);
+    #1;
+    #10000;
+    $finish;
+  end
+
+  reg [32-1:0] _tmp_0;
+  reg [32-1:0] xfsm;
+  localparam xfsm_init = 0;
+  localparam xfsm_1 = 1;
+  localparam xfsm_2 = 2;
+  localparam xfsm_3 = 3;
+  localparam xfsm_4 = 4;
+  localparam xfsm_5 = 5;
+  localparam xfsm_6 = 6;
+  localparam xfsm_7 = 7;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      xfsm <= xfsm_init;
+      _tmp_0 <= 0;
+    end else begin
+      case(xfsm)
+        xfsm_init: begin
+          if(reset_done) begin
+            xfsm <= xfsm_1;
+          end 
+        end
+        xfsm_1: begin
+          x <= (x + 1);
+          _tmp_0 <= (_tmp_0 + 1);
+          if((_tmp_0 == 10)) begin
+            xfsm <= xfsm_2;
+          end 
+        end
+        xfsm_2: begin
+          x <= 0;
+          xfsm <= xfsm_3;
+        end
+        xfsm_3: begin
+          xfsm <= xfsm_4;
+        end
+        xfsm_4: begin
+          xfsm <= xfsm_5;
+        end
+        xfsm_5: begin
+          xfsm <= xfsm_6;
+        end
+        xfsm_6: begin
+          xfsm <= xfsm_7;
+        end
+        xfsm_7: begin
+          $finish;
+        end
+      endcase
+    end
+  end
+
+  always @(posedge CLK) begin
+    if(reset_done) begin
+      $display("x=%d", x);
+      $display("y=%d", y);
+    end 
+  end
+
+endmodule
+
+
+module blinkled
+(
+  input CLK,
+  input RST,
+  input [32-1:0] x,
+  output [32-1:0] y,
+  input prst
+);
+
+  reg [32-1:0] _pipe_data_0;
+  reg [32-1:0] _pipe_data_1;
+  assign y = _pipe_data_1;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      _pipe_data_0 <= 0;
+      _pipe_data_1 <= 0;
+    end else begin
+      _pipe_data_0 <= _pipe_data_0 + x;
+      if(prst) begin
+        _pipe_data_0 <= 0;
+      end 
+      _pipe_data_1 <= _pipe_data_0;
+    end
+  end
+
+endmodule
+"""
+
+def test_led():
+    test_module = led.mkTest()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

sample/tests/lib_pipeline/acc_add/test_led.py

@@ -0,0 +1,100 @@
+import sys
+import os
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    x = m.Input('x', 32)
+    vx = m.Input('vx')
+    y = m.Output('y', 32)
+    vy = m.Output('vy')
+    prst = m.Input('prst')
+    
+    pipe = lib.Pipeline(m, 'pipe')
+
+    px = pipe.input(x, valid=vx)
+    psum = pipe.acc_add(px, initval=0, resetcond=prst)
+    psum.output(y, valid=vy)
+    
+    pipe.make_always(clk, rst)
+
+    return m
+
+def mkTest(numports=8):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+    
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+    x = ports['x']
+    vx = ports['vx']
+    y = ports['y']
+    vy = ports['vy']
+    prst = ports['prst']
+    
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    reset_done = m.Reg('reset_done', initval=0)
+    
+    reset_stmt = []
+    reset_stmt.append( reset_done(0) )
+    reset_stmt.append( prst(0) )
+    reset_stmt.append( x(0) )
+    reset_stmt.append( vx(0) )
+    
+    lib.simulation.setup_waveform(m, uut)
+    lib.simulation.setup_clock(m, clk, hperiod=5)
+    init = lib.simulation.setup_reset(m, rst, reset_stmt, period=100)
+
+    nclk = lib.simulation.next_clock
+    
+    init.add(
+        Delay(1000),
+        reset_done(1),
+        nclk(clk),
+        Delay(10000),
+        Systask('finish'),
+    )
+
+    x_count = m.TmpReg(32, initval=0)
+
+    xfsm = lib.FSM(m, 'xfsm')
+    xfsm.add(vx(0))
+    xfsm.goto_next(cond=reset_done)
+    xfsm.add(vx(1))
+    xfsm.add(x.inc())
+    xfsm.add(x_count.inc())
+    xfsm.goto_next(cond=x_count==10)
+    xfsm.add(vx(0))
+    
+    xfsm.make_always(clk, rst)
+    
+    
+    m.Always(Posedge(clk))(
+        If(reset_done)(
+            If(vx)(
+                Systask('display', 'x=%d', x)
+            ),
+            If(vy)(
+                Systask('display', 'y=%d', y)
+            )
+        )
+    )
+
+    return m
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)