some tests are correctly updated.

Author: shtaxxx

led.py

@@ -0,0 +1,39 @@
+import sys
+import os
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + 1)
+            )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(0)
+        ).Else(
+            If(count == 1024 - 1)(
+                led(led + 1)
+            )
+        ))
+    
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    # led.to_verilog(filename='tmp.v')
+    verilog = led.to_verilog()
+    print(verilog)

tests/cat/cat.py

@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
+
 from veriloggen import *
 
 def mkLed():

tests/cat/test_cat.py

@@ -1,4 +1,4 @@
-import led
+import cat
 
 expected_verilog = """
 module blinkled #
@@ -34,9 +34,9 @@
 endmodule
 """
 
-def test_led():
-    led_module = led.mkLed()
-    led_code = led_module.to_verilog()
+def test():
+    test_module = cat.mkLed()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -45,4 +45,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == led_code)
+    assert(expected_code == code)

tests/class/class.py renamed to tests/class/_class.py

@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
+
 from veriloggen import *
 
 class Led(Module):

tests/class/test_class.py

@@ -1,4 +1,4 @@
-import led
+import _class
 
 expected_verilog = """
 module blinkled #
@@ -34,9 +34,9 @@
 endmodule
 """
 
-def test_led():
-    led_module = led.Led()
-    led_code = led_module.to_verilog()
+def test():
+    test_module = _class.Led()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -45,4 +45,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == led_code)
+    assert(expected_code == code)

tests/cond/cond.py

@@ -1,5 +1,9 @@
 import sys
 import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
+
 from veriloggen import *
 
 def mkLed():

tests/cond/test_cond.py

@@ -1,4 +1,4 @@
-import led
+import cond
 
 expected_verilog = """
 module test #
@@ -73,8 +73,8 @@
 endmodule
 """
 
-def test_led():
-    test_module = led.mkTest()
+def test():
+    test_module = cond.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser

tests/for/for.py renamed to tests/for/_for.py

@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
+
 from veriloggen import *
 
 def mkLed():

tests/for/test_for.py

@@ -1,4 +1,4 @@
-import led
+import _for
 
 expected_verilog = """
 module blinkled #
@@ -31,9 +31,9 @@
 endmodule
 """
 
-def test_led():
-    led_module = led.mkLed()
-    led_code = led_module.to_verilog()
+def test():
+    test_module = _for.mkLed()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -42,4 +42,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == led_code)
+    assert(expected_code == code)

tests/function/function.py renamed to tests/function/_function.py

@@ -1,6 +1,9 @@
 import sys
 import os
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
+
 from veriloggen import *
 
 # external function definition