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Unused methods have been commented out.
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2 files changed

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-134
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‎pyverilog/dataflow/bindvisitor.py‎

Lines changed: 122 additions & 133 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
# Binding visitor
55
#
66
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
7-
# edited by ryosuke fukatani
87
# License: Apache 2.0
8+
# Contributor: ryosuke fukatani
99
#-------------------------------------------------------------------------------
1010
from __future__ import absolute_import
1111
from __future__ import print_function
@@ -256,11 +256,6 @@ def _createAlwaysinfo(self, node, scope):
256256
reset_name = None
257257
reset_bit = None
258258

259-
#TODO unimplemented
260-
#print('load: ' + str(self._first_lvalue_is_const(node)))
261-
#print('if_branch: ' + str(self._has_if_branch(node)))
262-
#print('reset_info: ' + str(self._get_rst_info(node)))
263-
264259
for l in node.sens_list.list:
265260
if l.sig is None:
266261
continue
@@ -288,133 +283,127 @@ def _createAlwaysinfo(self, node, scope):
288283

289284
return (clock_name, clock_edge, clock_bit, reset_name, reset_edge, reset_bit, senslist)
290285

291-
#TODO This function is implemented for https://github.com/PyHDI/Pyverilog/issues/14.
292-
#Be incorporated into formally in lator commit.
293-
def _first_lvalue_is_const(self, node):
294-
""" [FUNCTIONS]
295-
Walk until lvalue and judge whether it is constant or not.
296-
297-
ex.
298-
if(RST)
299-
reg1 <= 1'd0: //const: judged as rst branch
300-
301-
if(RST)
302-
reg1 <= {1'd0, 1'd0}: //const: judged as rst branch
303-
304-
if(RST)
305-
reg1 <= reg2: //variable: judged as not rst branch
306-
307-
if(RST)
308-
reg1 <= {1'd0, reg2}: //variable: judged as not rst branch
309-
"""
310-
if isinstance(node, Always):
311-
return self._first_lvalue_is_const(node.statement)
312-
elif isinstance(node, Block):
313-
return self._first_lvalue_is_const(node.statements[0])
314-
elif isinstance(node, IfStatement):
315-
return self._first_lvalue_is_const(node.true_statement)
316-
elif isinstance(node, NonblockingSubstitution):
317-
print(node.left.var)# for debug
318-
return self._first_lvalue_is_const(node.right)
319-
elif isinstance(node, Identifier):
320-
node_chain = self.get_scopechain(node)
321-
if node_chain in self.dataflow.terms.keys():
322-
#Parameter is regard as constant.
323-
return 'Parameter' in self.dataflow.terms[node_chain].termtype
324-
return False
325-
elif hasattr(node, 'children'):
326-
for child in node.children():
327-
if not self._first_lvalue_is_const(child):
328-
return False
329-
return True
330-
elif isinstance(node, Rvalue):
331-
return self._first_lvalue_is_const(node.var)
332-
elif hasattr(node, 'value'):
333-
return True
334-
else:
335-
raise Exception('Pyverilog unknown error')
336-
337-
def get_scopechain(self, node):
338-
assert isinstance(node, Identifier), 'Node type should be Identifier.'
339-
scope_list = self.frames.current.get_module_list() + [util.ScopeLabel(str(node)),]
340-
return util.ScopeChain(scope_list)
341-
342-
#TODO This function is implemented for https://github.com/PyHDI/Pyverilog/issues/14.
343-
#Be incorporated into formally in lator commit.
344-
def _get_rst_info(self, node, rst_name='', is_posedge=True, rst_bit=0):
345-
""" [FUNCTIONS]
346-
get reset information from first if statement.
347-
348-
ex1.
349-
always @(posedge CLK or posedge RST) begin
350-
if(RST)
351-
reg1 <= 0;
352-
else
353-
reg1 <= !reg1;
354-
end
355-
->RST is posedge RST.
356-
357-
ex2.
358-
always @(posedge CLK or posedge RST) begin
359-
if(!RSTN[1])
360-
reg1 <= 0;
361-
else
362-
reg1 <= !reg1;
363-
end
364-
->RSTN[1] is negedge RST.
365-
366-
ex3.
367-
always @(posedge CLK or posedge RST) begin
368-
if(RST && RST2)
369-
reg1 <= 0;
370-
else
371-
reg1 <= !reg1;
372-
end
373-
-> reg1 has no reset. (too complex condition)
374-
"""
375-
if isinstance(node, Always):
376-
return self._get_rst_info(node.statement, rst_name, is_posedge, rst_bit)
377-
elif isinstance(node, Block):
378-
return self._get_rst_info(node.statements[0], rst_name, is_posedge, rst_bit)
379-
elif isinstance(node, IfStatement):
380-
return self._get_rst_info(node.cond, rst_name, is_posedge, rst_bit)
381-
elif isinstance(node, pyverilog.vparser.ast.Ulnot):
382-
is_posedge = not is_posedge
383-
return self._get_rst_info(node.children()[0], rst_name, is_posedge, rst_bit)
384-
elif isinstance(node, pyverilog.vparser.ast.Pointer):
385-
#TODO if identifier
386-
if isinstance(node.ptr, Identifier):
387-
ptr_chain = self.get_scopechain(node.ptr)
388-
if 'Parameter' in self.dataflow.terms[ptr_chain].termtype:
389-
rst_bit = self.dataflow.binddict[ptr_chain][0].tree.eval()
390-
return self._get_rst_info(node.var, rst_name, is_posedge, rst_bit)
391-
else:
392-
return (None, None, None)
393-
elif hasattr(node.ptr, 'value'):
394-
return self._get_rst_info(node.var, rst_name, is_posedge, int(node.ptr.value))
395-
elif isinstance(node, pyverilog.vparser.ast.Identifier):
396-
return (node, is_posedge, rst_bit)
397-
return (None, None, None)
398-
399-
#TODO This function is implemented for https://github.com/PyHDI/Pyverilog/issues/14.
400-
#Be incorporated into formally in lator commit.
401-
def _has_if_branch(self, node):
402-
""" [FUNCTIONS]
403-
Return always block have 'if branch' or not.
404-
ex.
405-
always @(posedge CLK or posedge RST) begin
406-
reg1 <= 0;
407-
end
408-
-> reg1 has no reset. (If statement isn't exists.)
409-
"""
410-
if isinstance(node, Always):
411-
return self._has_if_branch(node.statement)
412-
elif isinstance(node, Block):
413-
return self._has_if_branch(node.statements[0])
414-
elif isinstance(node, IfStatement):
415-
return True
416-
else:
417-
return False
286+
#def _first_lvalue_is_const(self, node):
287+
# """ [FUNCTIONS]
288+
# Walk until lvalue and judge whether it is constant or not.
289+
#
290+
# ex.
291+
# if(RST)
292+
# reg1 <= 1'd0: //const: judged as rst branch
293+
#
294+
# if(RST)
295+
# reg1 <= {1'd0, 1'd0}: //const: judged as rst branch
296+
#
297+
# if(RST)
298+
# reg1 <= reg2: //variable: judged as not rst branch
299+
#
300+
# if(RST)
301+
# reg1 <= {1'd0, reg2}: //variable: judged as not rst branch
302+
# """
303+
# if isinstance(node, Always):
304+
# return self._first_lvalue_is_const(node.statement)
305+
# elif isinstance(node, Block):
306+
# return self._first_lvalue_is_const(node.statements[0])
307+
# elif isinstance(node, IfStatement):
308+
# return self._first_lvalue_is_const(node.true_statement)
309+
# elif isinstance(node, NonblockingSubstitution):
310+
# print(node.left.var)# for debug
311+
# return self._first_lvalue_is_const(node.right)
312+
# elif isinstance(node, Identifier):
313+
# node_chain = self.get_scopechain(node)
314+
# if node_chain in self.dataflow.terms.keys():
315+
# #Parameter is regard as constant.
316+
# return 'Parameter' in self.dataflow.terms[node_chain].termtype
317+
# return False
318+
# elif hasattr(node, 'children'):
319+
# for child in node.children():
320+
# if not self._first_lvalue_is_const(child):
321+
# return False
322+
# return True
323+
# elif isinstance(node, Rvalue):
324+
# return self._first_lvalue_is_const(node.var)
325+
# elif hasattr(node, 'value'):
326+
# return True
327+
# else:
328+
# raise Exception('Pyverilog unknown error')
329+
330+
#def get_scopechain(self, node):
331+
# assert isinstance(node, Identifier), 'Node type should be Identifier.'
332+
# scope_list = self.frames.current.get_module_list() + [util.ScopeLabel(str(node)),]
333+
# return util.ScopeChain(scope_list)
334+
335+
#def _get_rst_info(self, node, rst_name='', is_posedge=True, rst_bit=0):
336+
# """ [FUNCTIONS]
337+
# get reset information from first if statement.
338+
#
339+
# ex1.
340+
# always @(posedge CLK or posedge RST) begin
341+
# if(RST)
342+
# reg1 <= 0;
343+
# else
344+
# reg1 <= !reg1;
345+
# end
346+
# ->RST is posedge RST.
347+
#
348+
# ex2.
349+
# always @(posedge CLK or posedge RST) begin
350+
# if(!RSTN[1])
351+
# reg1 <= 0;
352+
# else
353+
# reg1 <= !reg1;
354+
# end
355+
# ->RSTN[1] is negedge RST.
356+
#
357+
# ex3.
358+
# always @(posedge CLK or posedge RST) begin
359+
# if(RST && RST2)
360+
# reg1 <= 0;
361+
# else
362+
# reg1 <= !reg1;
363+
# end
364+
# -> reg1 has no reset. (too complex condition)
365+
# """
366+
# if isinstance(node, Always):
367+
# return self._get_rst_info(node.statement, rst_name, is_posedge, rst_bit)
368+
# elif isinstance(node, Block):
369+
# return self._get_rst_info(node.statements[0], rst_name, is_posedge, rst_bit)
370+
# elif isinstance(node, IfStatement):
371+
# return self._get_rst_info(node.cond, rst_name, is_posedge, rst_bit)
372+
# elif isinstance(node, pyverilog.vparser.ast.Ulnot):
373+
# is_posedge = not is_posedge
374+
# return self._get_rst_info(node.children()[0], rst_name, is_posedge, rst_bit)
375+
# elif isinstance(node, pyverilog.vparser.ast.Pointer):
376+
# #TODO if identifier
377+
# if isinstance(node.ptr, Identifier):
378+
# ptr_chain = self.get_scopechain(node.ptr)
379+
# if 'Parameter' in self.dataflow.terms[ptr_chain].termtype:
380+
# rst_bit = self.dataflow.binddict[ptr_chain][0].tree.eval()
381+
# return self._get_rst_info(node.var, rst_name, is_posedge, rst_bit)
382+
# else:
383+
# return (None, None, None)
384+
# elif hasattr(node.ptr, 'value'):
385+
# return self._get_rst_info(node.var, rst_name, is_posedge, int(node.ptr.value))
386+
# elif isinstance(node, pyverilog.vparser.ast.Identifier):
387+
# return (node, is_posedge, rst_bit)
388+
# return (None, None, None)
389+
390+
#def _has_if_branch(self, node):
391+
# """ [FUNCTIONS]
392+
# Return always block have 'if branch' or not.
393+
# ex.
394+
# always @(posedge CLK or posedge RST) begin
395+
# reg1 <= 0;
396+
# end
397+
# -> reg1 has no reset. (If statement isn't exists.)
398+
# """
399+
# if isinstance(node, Always):
400+
# return self._has_if_branch(node.statement)
401+
# elif isinstance(node, Block):
402+
# return self._has_if_branch(node.statements[0])
403+
# elif isinstance(node, IfStatement):
404+
# return True
405+
# else:
406+
# return False
418407

419408
def visit_IfStatement(self, node):
420409
if self.frames.isFunctiondef() and not self.frames.isFunctioncall(): return

‎pyverilog/dataflow/dataflow.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
# Basic classes of Data flow nodes
55
#
66
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
7-
# modified by ryoduke fukatani
87
# License: Apache 2.0
8+
# Contributor: ryosuke fukatani
99
#-------------------------------------------------------------------------------
1010
from __future__ import absolute_import
1111
from __future__ import print_function

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