Refactoring for the release.

Author: shtaxxx

pyverilog/vparser/ast.py

@@ -1,11 +1,11 @@
 #-------------------------------------------------------------------------------
 # ast.py
 #
-# Verilog HDL AST classes with Pyverilog
+# Verilog HDL AST Node Definitions
 #
 # Copyright (C) 2013, Shinya Takamaeda-Yamazaki
-# edited by ryosuke fukatani
 # License: Apache 2.0
+# Contributor: ryosuke fukatani
 #-------------------------------------------------------------------------------
 from __future__ import absolute_import
 from __future__ import print_function
@@ -770,4 +770,3 @@ def children(self):
         nodelist = []
         if self.statement: nodelist.append(self.statement)
         return tuple(nodelist)
-

pyverilog/vparser/lexer.py

@@ -4,8 +4,8 @@
 # Verilog Lexical Analyzer
 #
 # Copyright (C) 2013, Shinya Takamaeda-Yamazaki
-# Edited by ryosuke fukatani
 # License: Apache 2.0
+# Contributor: ryosuke fukatani
 #-------------------------------------------------------------------------------
 from __future__ import absolute_import
 from __future__ import print_function
@@ -321,8 +321,8 @@ def showVersion():
         showVersion()
 
     text = preprocess(filelist, 
-                      preprocess_include=options.include,
-                      preprocess_define=options.define)
+                      include=options.include,
+                      define=options.define)
 
     dump = dump_tokens(text)
 

pyverilog/vparser/parser.py

@@ -1,11 +1,11 @@
 #-------------------------------------------------------------------------------
 # parser.py
 #
-# Parser
+# Verilog Parser
 #
 # Copyright (C) 2013, Shinya Takamaeda-Yamazaki
-# modified by ryosuke fukatani
 # License: Apache 2.0
+# Contributor: ryosuke fukatani
 #-------------------------------------------------------------------------------
 from __future__ import absolute_import
 from __future__ import print_function