absolute_import and print_function are added for all tests.

shtaxxx · shtaxxx · commit e05ef8c48fe9 · 2015-11-20T13:03:18.000+09:00
diff --git a/tests/ast_code_generator_test/test_ast_always.py b/tests/ast_code_generator_test/test_ast_always.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 
diff --git a/tests/ast_code_generator_test/test_ast_assign.py b/tests/ast_code_generator_test/test_ast_assign.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 
diff --git a/tests/dataflow_test/test_dat_blocking.py b/tests/dataflow_test/test_dat_blocking.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_case.py b/tests/dataflow_test/test_dat_case.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_case_in_func.py b/tests/dataflow_test/test_dat_case_in_func.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_casex.py b/tests/dataflow_test/test_dat_casex.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_decimal.py b/tests/dataflow_test/test_dat_decimal.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_decimal_signed.py b/tests/dataflow_test/test_dat_decimal_signed.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_decimal_width.py b/tests/dataflow_test/test_dat_decimal_width.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_function.py b/tests/dataflow_test/test_dat_function.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_generate.py b/tests/dataflow_test/test_dat_generate.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_generate_instance.py b/tests/dataflow_test/test_dat_generate_instance.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_led.py b/tests/dataflow_test/test_dat_led.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_partial.py b/tests/dataflow_test/test_dat_partial.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_partselect_assign.py b/tests/dataflow_test/test_dat_partselect_assign.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_primitive.py b/tests/dataflow_test/test_dat_primitive.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_ptr_clock_reset.py b/tests/dataflow_test/test_dat_ptr_clock_reset.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_reset.py b/tests/dataflow_test/test_dat_reset.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_signed_task.py b/tests/dataflow_test/test_dat_signed_task.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/dataflow_test/test_dat_supply.py b/tests/dataflow_test/test_dat_supply.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
diff --git a/tests/parser_test/test_par_delay.py b/tests/parser_test/test_par_delay.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.vparser.parser import VerilogCodeParser
diff --git a/tests/parser_test/test_par_escape.py b/tests/parser_test/test_par_escape.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.vparser.parser import VerilogCodeParser
diff --git a/tests/parser_test/test_par_instance_array.py b/tests/parser_test/test_par_instance_array.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.vparser.parser import VerilogCodeParser
diff --git a/tests/parser_test/test_par_led_main.py b/tests/parser_test/test_par_led_main.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.vparser.parser import VerilogCodeParser
diff --git a/tests/preprocessor_test/test_pre_led_main.py b/tests/preprocessor_test/test_pre_led_main.py
@@ -1,3 +1,5 @@
+from __future__ import absolute_import
+from __future__ import print_function
 import os
 import sys
 from pyverilog.vparser.preprocessor import VerilogPreprocessor

Original file line number	Diff line number	Diff line change
`@@ -1,3 +1,5 @@`
	`1`	`+from __future__ import absolute_import`
	`2`	`+from __future__ import print_function`
`1`	`3`	`import os`
`2`	`4`	`import sys`
`3`	`5`