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ast_code_generator: apply rule of del_paren is refactored.
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-12
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+8
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pyverilog/ast_code_generator/codegen.py

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -459,17 +459,15 @@ def visit_Operator(self, node):
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rorder = op2order(node.right.__class__.__name__)
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left = self.visit(node.left)
461461
right = self.visit(node.right)
462-
if ( isinstance(node.left, (Identifier, Value)) or
463-
((not isinstance(node.left, (Sll, Srl, Sra,
464-
LessThan, GreaterThan, LessEq, GreaterEq,
465-
Eq, NotEq, Eql, NotEql))) and
466-
(lorder is not None and lorder <= order)) ):
462+
if ((not isinstance(node.left, (Sll, Srl, Sra,
463+
LessThan, GreaterThan, LessEq, GreaterEq,
464+
Eq, NotEq, Eql, NotEql))) and
465+
(lorder is not None and lorder <= order)):
467466
left = del_paren(left)
468-
if ( isinstance(node.right, (Identifier, Value)) or
469-
((not isinstance(node.right, (Sll, Srl, Sra,
470-
LessThan, GreaterThan, LessEq, GreaterEq,
471-
Eq, NotEq, Eql, NotEql))) and
472-
(rorder is not None and order > rorder)) ):
467+
if ((not isinstance(node.right, (Sll, Srl, Sra,
468+
LessThan, GreaterThan, LessEq, GreaterEq,
469+
Eq, NotEq, Eql, NotEql))) and
470+
(rorder is not None and order > rorder)):
473471
right = del_paren(right)
474472
template_dict = {
475473
'left' : left,
@@ -483,8 +481,6 @@ def visit_UnaryOperator(self, node):
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filename = getfilename(node)
484482
template = self.env.get_template(filename)
485483
right = self.visit(node.right)
486-
if isinstance(node.right, (Identifier, Value)):
487-
right = del_paren(right)
488484
template_dict = {
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'right' : right,
490486
'op' : op2mark(node.__class__.__name__),

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