ast_code_generator: Redundant spaces are removed from the text results of Width, Length, and Partselect.

Author: shtaxxx

pyverilog/ast_code_generator/codegen.py

@@ -61,6 +61,9 @@ def del_paren(s):
         return s[1:-1]
     return s
 
+def del_space(s):
+    return s.replace(' ', '')
+
 class ASTCodeGenerator(ConvertVisitor):
     def __init__(self, indentsize=2):
         self.env = Environment(loader=FileSystemLoader(DEFAULT_TEMPLATE_DIR))
@@ -133,8 +136,8 @@ def visit_Width(self, node):
         filename = getfilename(node)
         template = self.env.get_template(filename)
         template_dict = {
-            'msb' : del_paren(self.visit(node.msb)),
-            'lsb' : del_paren(self.visit(node.lsb)),
+            'msb' : del_space(del_paren(self.visit(node.msb))),
+            'lsb' : del_space(del_paren(self.visit(node.lsb))),
             }
         rslt = template.render(template_dict)
         return rslt
@@ -143,8 +146,8 @@ def visit_Length(self, node):
         filename = getfilename(node)
         template = self.env.get_template(filename)
         template_dict = {
-            'msb' : del_paren(self.visit(node.msb)),
-            'lsb' : del_paren(self.visit(node.lsb)),
+            'msb' : del_space(del_paren(self.visit(node.msb))),
+            'lsb' : del_space(del_paren(self.visit(node.lsb))),
             }
         rslt = template.render(template_dict)
         return rslt
@@ -417,8 +420,8 @@ def visit_Partselect(self, node):
         template = self.env.get_template(filename)
         template_dict = {
             'var' : self.visit(node.var),
-            'msb' : del_paren(self.visit(node.msb)),
-            'lsb' : del_paren(self.visit(node.lsb)),
+            'msb' : del_space(del_paren(self.visit(node.msb))),
+            'lsb' : del_space(del_paren(self.visit(node.lsb))),
             }
         rslt = template.render(template_dict)
         return rslt

pyverilog/ast_code_generator/template/length.txt

@@ -1 +1 @@
-[{{ msb }} : {{ lsb }}]
+[{{ msb }}:{{ lsb }}]

pyverilog/ast_code_generator/template/partselect.txt

@@ -1 +1 @@
-{{ var }}[{{ msb }} : {{ lsb }}]
+{{ var }}[{{ msb }}:{{ lsb }}]

pyverilog/ast_code_generator/template/width.txt

@@ -1 +1 @@
-[{{ msb }} : {{ lsb }}]
+[{{ msb }}:{{ lsb }}]

tests/ast_code_generator_test/test_ast_always.py

@@ -15,11 +15,11 @@
 (
   input CLK,
   input RST,
-  output [7 : 0] led
+  output [7:0] led
 );
 
-  reg [DATAWID - 1 : 0] count;
-  assign led = count[DATAWID - 1 : DATAWID - 8];
+  reg [DATAWID-1:0] count;
+  assign led = count[DATAWID-1:DATAWID-8];
 
   always @(posedge CLK) begin
     if(RST) begin

tests/ast_code_generator_test/test_ast_assign.py

@@ -12,7 +12,7 @@
 (
   input CLK,
   input RST,
-  output [7 : 0] led
+  output [7:0] led
 );
 
   assign led = 8;