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main parts of pyverilog modules are moved to examples.
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‎examples/Makefile‎

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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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PREPROCESSOR=example_preprocessor.py
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LEXER=example_lexer.py
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PARSER=example_parser.py
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DATAFLOW=example_dataflow_analyzer.py
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OPTIMIZER=example_optimizer.py
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MERGE=example_merge.py
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WALKER=example_walker.py
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SUBSET=example_subset.py
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DFCODEGEN=example_dataflow_codegen.py
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GRAPHGEN=example_graphgen.py
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CONTROLFLOW=example_controlflow_analyzer.py
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ACTIVE=example_active_analyzer.py
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ACTIVERANGE=example_active_range.py
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CODEGEN=example_codegen.py
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SRCS=../verilogcode/vectoradd.v
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TOP=-t TOP
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TARGETS=-s "TOP.MEM_A"
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CODEGEN_OUT=out.v
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CODEGEN_OPT=-o $(CODEGEN_OUT)
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GRAPHGEN_OUT=out.png
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GRAPHGEN_OPT=--identical --walk --step=0 -o $(GRAPHGEN_OUT)
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NOGRAPH=--nograph
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NOLABEL=--nolabel
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CONTROLFLOW_OPT=$(NOGRAPH) $(NOLABEL)
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.PHONY: all
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all: preprocess lex parse dataflow optimize merge walk subset dfcodegen \
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controlflow active activerange codegen
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.PHONY: preprocess
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preprocess:
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$(PYTHON) $(OPT) $(PREPROCESSOR) $(SRCS)
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.PHONY: lex
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lex:
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$(PYTHON) $(OPT) $(LEXER) $(SRCS)
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.PHONY: parse
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parse:
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$(PYTHON) $(OPT) $(PARSER) $(SRCS)
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.PHONY: dataflow
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dataflow:
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$(PYTHON) $(OPT) $(DATAFLOW) $(SRCS) $(TOP)
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.PHONY: optimize
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optimize:
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$(PYTHON) $(OPT) $(OPTIMIZER) $(SRCS) $(TOP)
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.PHONY: merge
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merge:
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$(PYTHON) $(OPT) $(MERGE) $(SRCS) $(TOP) $(TARGETS)
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.PHONY: walk
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walk:
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$(PYTHON) $(OPT) $(WALKER) $(SRCS) $(TOP) $(TARGETS)
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.PHONY: subset
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subset:
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$(PYTHON) $(OPT) $(SUBSET) $(SRCS) $(TOP) $(TARGETS)
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.PHONY: dfcodegen
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dfcodegen:
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$(PYTHON) $(OPT) $(DFCODEGEN) $(SRCS) $(TOP) $(TARGETS) $(CODEGEN_OPT)
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.PHONY: graphgen
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graphgen:
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$(PYTHON) $(OPT) $(GRAPHGEN) $(SRCS) $(TOP) $(TARGETS) $(GRAPHGEN_OPT)
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.PHONY: controlflow
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controlflow:
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$(PYTHON) $(OPT) $(CONTROLFLOW) $(SRCS) $(TOP) $(TARGETS) $(CONTROLFLOW_OPT)
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.PHONY: active
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active:
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$(PYTHON) $(OPT) $(ACTIVE) $(TOP) $(SRCS) $(TARGETS)
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.PHONY: activerange
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activerange:
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$(PYTHON) $(OPT) $(ACTIVERANGE) $(TOP) $(SRCS) $(TARGETS)
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.PHONY: codegen
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codegen:
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$(PYTHON) $(OPT) $(CODEGEN) $(SRCS)
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py *.out *.png *.v *.dot

‎examples/example_active_analyzer.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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from optparse import OptionParser
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
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import pyverilog.utils.version
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import pyverilog.utils.util as util
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import pyverilog.controlflow.splitter as splitter
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from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
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from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
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from pyverilog.controlflow.active_analyzer import VerilogActiveConditionAnalyzer
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def main():
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INFO = "Active condition analyzer"
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VERSION = pyverilog.utils.version.VERSION
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USAGE = "Usage: python active_analyzer.py -t TOPMODULE file ..."
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def showVersion():
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print(INFO)
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print(VERSION)
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print(USAGE)
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sys.exit()
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optparser = OptionParser()
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optparser.add_option("-v","--version",action="store_true",dest="showversion",
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default=False,help="Show the version")
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optparser.add_option("-t","--top",dest="topmodule",
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default="TOP",help="Top module, Default=TOP")
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optparser.add_option("-s","--search",dest="searchtarget",action="append",
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default=[],help="Search Target Signal")
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(options, args) = optparser.parse_args()
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filelist = args
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if options.showversion:
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showVersion()
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for f in filelist:
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if not os.path.exists(f): raise IOError("file not found: " + f)
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if len(filelist) == 0:
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showVersion()
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analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
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analyzer.generate()
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directives = analyzer.get_directives()
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terms = analyzer.getTerms()
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binddict = analyzer.getBinddict()
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optimizer = VerilogDataflowOptimizer(terms, binddict)
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optimizer.resolveConstant()
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resolved_terms = optimizer.getResolvedTerms()
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resolved_binddict = optimizer.getResolvedBinddict()
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constlist = optimizer.getConstlist()
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canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict,
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resolved_terms, resolved_binddict, constlist)
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for target in options.searchtarget:
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signal = util.toTermname(target)
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active_conditions = canalyzer.getActiveConditions( signal )
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#active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_modify )
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#active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_unmodify )
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print('Active Cases: %s' % signal)
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for fsm_sig, active_conditions in sorted(active_conditions.items(), key=lambda x:str(x[0])):
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print('FSM: %s' % fsm_sig)
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for state, active_condition in sorted(active_conditions, key=lambda x:str(x[0])):
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s = []
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s.append('state: %d -> ' % state)
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if active_condition: s.append(active_condition.tocode())
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else: s.append('empty')
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print(''.join(s))
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if __name__ == '__main__':
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main()

‎examples/example_active_range.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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from optparse import OptionParser
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
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import pyverilog.utils.version
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import pyverilog.utils.util as util
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from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
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from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
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from pyverilog.controlflow.active_range import VerilogActiveAnalyzer
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def main():
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INFO = "Active condition analyzer (Obsoluted)"
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VERSION = pyverilog.utils.version.VERSION
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USAGE = "Usage: python active_range.py -t TOPMODULE file ..."
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def showVersion():
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print(INFO)
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print(VERSION)
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print(USAGE)
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sys.exit()
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optparser = OptionParser()
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optparser.add_option("-v","--version",action="store_true",dest="showversion",
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default=False,help="Show the version")
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optparser.add_option("-t","--top",dest="topmodule",
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default="TOP",help="Top module, Default=TOP")
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optparser.add_option("-s","--search",dest="searchtarget",action="append",
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default=[],help="Search Target Signal")
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(options, args) = optparser.parse_args()
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filelist = args
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if options.showversion:
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showVersion()
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for f in filelist:
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if not os.path.exists(f): raise IOError("file not found: " + f)
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if len(filelist) == 0:
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showVersion()
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analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
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analyzer.generate()
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directives = analyzer.get_directives()
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terms = analyzer.getTerms()
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binddict = analyzer.getBinddict()
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optimizer = VerilogDataflowOptimizer(terms, binddict)
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optimizer.resolveConstant()
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resolved_terms = optimizer.getResolvedTerms()
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resolved_binddict = optimizer.getResolvedBinddict()
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constlist = optimizer.getConstlist()
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aanalyzer = VerilogActiveAnalyzer(options.topmodule, terms, binddict,
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resolved_terms, resolved_binddict, constlist)
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for target in options.searchtarget:
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signal = util.toTermname(target)
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print('Active Conditions: %s' % signal)
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active_conditions = aanalyzer.getActiveConditions( signal )
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print(sorted(active_conditions, key=lambda x:str(x)))
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print('Changed Conditions')
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changed_conditions = aanalyzer.getChangedConditions( signal )
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print(sorted(changed_conditions, key=lambda x:str(x)))
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print('Changed Condition Dict')
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changed_conditiondict = aanalyzer.getChangedConditionsWithAssignments( signal )
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print(sorted(changed_conditiondict.items(), key=lambda x:str(x[0])))
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print('Unchanged Conditions')
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unchanged_conditions = aanalyzer.getUnchangedConditions( signal )
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print(sorted(unchanged_conditions, key=lambda x:str(x)))
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if __name__ == '__main__':
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main()

‎examples/example_ast_code.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
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import pyverilog.vparser.ast as vast
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
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def main():
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params = vast.Paramlist(())
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clk = vast.Ioport( vast.Input('CLK') )
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rst = vast.Ioport( vast.Input('RST') )
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width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
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led = vast.Ioport( vast.Output('led', width=width) )
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ports = vast.Portlist( (clk, rst, led) )
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items = ( vast.Assign( vast.Identifier('led'), vast.IntConst('8') ) ,)
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ast = vast.ModuleDef("top", params, ports, items)
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codegen = ASTCodeGenerator()
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rslt = codegen.visit(ast)
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print(rslt)
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if __name__ == '__main__':
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main()

‎examples/example_codegen.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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from optparse import OptionParser
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
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import pyverilog.utils.version
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from pyverilog.vparser.parser import VerilogCodeParser
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
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def main():
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INFO = "Code converter from AST"
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VERSION = pyverilog.utils.version.VERSION
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USAGE = "Usage: python codegen.py file ..."
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def showVersion():
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print(INFO)
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print(VERSION)
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print(USAGE)
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sys.exit()
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optparser = OptionParser()
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optparser.add_option("-v","--version",action="store_true",dest="showversion",
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default=False,help="Show the version")
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optparser.add_option("-I","--include",dest="include",action="append",
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default=[],help="Include path")
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optparser.add_option("-D",dest="define",action="append",
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default=[],help="Macro Definition")
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(options, args) = optparser.parse_args()
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filelist = args
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if options.showversion:
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showVersion()
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for f in filelist:
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if not os.path.exists(f): raise IOError("file not found: " + f)
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if len(filelist) == 0:
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showVersion()
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codeparser = VerilogCodeParser(filelist,
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preprocess_include=options.include,
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preprocess_define=options.define)
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ast = codeparser.parse()
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directives = codeparser.get_directives()
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codegen = ASTCodeGenerator()
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rslt = codegen.visit(ast)
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print(rslt)
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if __name__ == '__main__':
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main()

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