Skip to content

Commit 16c8fe4

Browse files
committed
Unnecessary sys.path.insert is removed.
1 parent 5386c32 commit 16c8fe4

25 files changed

+24
-52
lines changed

pyverilog/ast_code_generator/codegen.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,8 @@
1515
import functools
1616
from jinja2 import Environment, FileSystemLoader
1717

18-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
18+
if __name__ == '__main__':
19+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
1920

2021
import pyverilog.utils.version
2122
from pyverilog.vparser.parser import VerilogCodeParser

pyverilog/controlflow/active_analyzer.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,13 @@
66
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
77
# License: Apache 2.0
88
#-------------------------------------------------------------------------------
9-
109
from __future__ import absolute_import
1110
from __future__ import print_function
1211
import sys
1312
import os
1413

15-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
14+
if __name__ == '__main__':
15+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
1616

1717
import pyverilog.utils.version
1818
import pyverilog.utils.util as util

pyverilog/controlflow/active_range.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,13 @@
66
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
77
# License: Apache 2.0
88
#-------------------------------------------------------------------------------
9-
109
from __future__ import absolute_import
1110
from __future__ import print_function
1211
import sys
1312
import os
1413

15-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
14+
if __name__ == '__main__':
15+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
1616

1717
import pyverilog.utils.version
1818
import pyverilog.utils.util as util

pyverilog/controlflow/controlflow_analyzer.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,13 @@
88
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
99
# License: Apache 2.0
1010
#-------------------------------------------------------------------------------
11-
1211
from __future__ import absolute_import
1312
from __future__ import print_function
1413
import sys
1514
import os
1615

17-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
16+
if __name__ == '__main__':
17+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
1818

1919
import pyverilog.utils.version
2020
import pyverilog.utils.util as util

pyverilog/controlflow/splitter.py

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,14 +6,11 @@
66
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
77
# License: Apache 2.0
88
#-------------------------------------------------------------------------------
9-
109
from __future__ import absolute_import
1110
from __future__ import print_function
1211
import sys
1312
import os
1413

15-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
16-
1714
import pyverilog.utils.signaltype as signaltype
1815
from pyverilog.dataflow.dataflow import *
1916

pyverilog/controlflow/transition.py

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,14 +6,11 @@
66
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
77
# License: Apache 2.0
88
#-------------------------------------------------------------------------------
9-
109
from __future__ import absolute_import
1110
from __future__ import print_function
1211
import sys
1312
import os
1413

15-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
16-
1714
from pyverilog.dataflow.dataflow import *
1815
import pyverilog.utils.util as util
1916
import pyverilog.utils.signaltype as signaltype

pyverilog/dataflow/bindvisitor.py

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,6 @@
1313
import os
1414
import re
1515

16-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
17-
1816
from pyverilog.vparser.ast import *
1917
import pyverilog.utils.util as util
2018
import pyverilog.utils.verror as verror

pyverilog/dataflow/codegen.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,8 @@
1212
import os
1313
import re
1414

15-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
15+
if __name__ == '__main__':
16+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
1617

1718
import pyverilog.utils.version
1819
import pyverilog.utils.util as util

pyverilog/dataflow/dataflow.py

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,6 @@
1414
import re
1515
import copy
1616

17-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
18-
1917
import pyverilog.utils.verror as verror
2018
import pyverilog.utils.util as util
2119
import pyverilog.utils.signaltype as signaltype

pyverilog/dataflow/dataflow_analyzer.py

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,11 @@
1212
import os
1313
import subprocess
1414

15-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
15+
if __name__ == '__main__':
16+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
17+
1618
sys.setrecursionlimit(16 * 1024)
1719

18-
import pyverilog
19-
import pyverilog.utils
2020
import pyverilog.utils.version
2121
from pyverilog.vparser.parser import VerilogCodeParser
2222
from pyverilog.dataflow.modulevisitor import ModuleVisitor

0 commit comments

Comments
 (0)