dataflow_analyzer supports the basic primitives, such as 'and', 'or', and 'not'.

Author: shtaxxx

pyverilog/dataflow/bindvisitor.py

@@ -135,7 +135,24 @@ def visit_Task(self, node):
         self.generic_visit(node)
         self.frames.unsetTaskDef()
 
+    def _visit_Instance_primitive(self, node):
+        primitive_type = primitives[node.module]
+        left = node.portlist[0].argname
+        right = None
+        if primitive_type == None:
+            right = Partselect(node.portlist[1].argname, IntConst('0'), IntConst('0'))
+        elif primitive_type == Unot:
+            right = Ulnot(Partselect(node.portlist[1].argname, IntConst('0'), IntConst('0')))
+        else:
+            concat_list = [Partselect(p.argname, IntConst('0'), IntConst('0')) for p in node.portlist[1:]]
+            right = primitive_type(Concat(concat_list))
+        self.addBind(left, right, bindtype='assign')
+        
     def visit_Instance(self, node):
+        if node.module in primitives:
+            self._visit_Instance_primitive(node)
+            return
+        
         current = self.stackInstanceFrame(node.name, node.module)
 
         scope = self.frames.getCurrent()

pyverilog/dataflow/signalvisitor.py

@@ -117,6 +117,8 @@ def visit_Initial(self, node):
         #self.frames.setCurrent(current)
 
     def visit_Instance(self, node):
+        if node.module in primitives: return
+        
         current = self.stackInstanceFrame(node.name, node.module)
 
         self.setInstanceSimpleConstantTerms()

pyverilog/dataflow/visit.py

@@ -24,6 +24,20 @@
 map_key   = lambda f,d: collections.OrderedDict([ (f(k),v) for k,v in d.items() ])
 map_value = lambda f,d: collections.OrderedDict([ (k,f(v)) for k,v in d.items() ])
 
+################################################################################
+# Primitive list
+################################################################################
+primitives = {
+    'and' : Uand,
+    'nand': Unand,
+    'or' : Uor,
+    'nor' : Unor,
+    'xor' : Uxor,
+    'xnor' : Uxnor,
+    'not' : Unot,
+    'buf' : None
+}
+
 ################################################################################
 # Base Visitor
 ################################################################################

pyverilog/testcode/primitive.v

@@ -0,0 +1,21 @@
+module TOP 
+  (
+   CLK, RST,
+   in1, in2, in3, in4,
+   out0, out1, out2, out3, out4, out5, out6, out7
+   );
+  
+  input CLK, RST;
+  input in1, in2, in3, in4;
+  output out0, out1, out2, out3, out4, out5, out6, out7;
+ 
+  and  U0 (out0, in1, in2, in3, in4);
+  nand U1 (out1, in1, in2, in3, in4);
+  or   U2 (out2, in1, in2, in3, in4);
+  nor  U3 (out3, in1, in2, in3, in4);
+  xor  U4 (out4, in1, in2, in3, in4);
+  xnor U5 (out5, in1, in2, in3, in4);
+  not  U6 (out6, in1);
+  buf  U7 (out7, in1);
+endmodule
+

pyverilog/vparser/ast.py

@@ -648,16 +648,16 @@ def children(self):
         if self.statement: nodelist.extend(self.statement)
         return tuple(nodelist)
 
-#class TaskCall(Node):
-#    attr_names = ()
-#    def __init__(self, name, args):
-#        self.name = name
-#        self.args = args
-#    def children(self):
-#        nodelist = []
-#        if self.name: nodelist.append(self.name)
-#        if self.args: nodelist.extend(self.args)
-#        return tuple(nodelist)
+class TaskCall(Node):
+    attr_names = ()
+    def __init__(self, name, args):
+        self.name = name
+        self.args = args
+    def children(self):
+        nodelist = []
+        if self.name: nodelist.append(self.name)
+        if self.args: nodelist.extend(self.args)
+        return tuple(nodelist)
 
 class GenerateStatement(Node):
     attr_names = ()