Skip to content

Commit 3e5f54d

Browse files
committed
"or" primitive module is supported in vparser.
1 parent 6852e31 commit 3e5f54d

File tree

1 file changed

+8
-0
lines changed

1 file changed

+8
-0
lines changed

pyverilog/vparser/parser.py

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -111,6 +111,10 @@ def p_modulename(self, p):
111111
'modulename : ID'
112112
p[0] = p[1]
113113

114+
def p_modulename_or(self, p):
115+
'modulename : SENS_OR' # or primitive
116+
p[0] = p[1]
117+
114118
def p_paramlist(self, p):
115119
'paramlist : DELAY LPAREN params RPAREN'
116120
p[0] = Paramlist(params=p[3])
@@ -1311,6 +1315,10 @@ def p_instance(self, p):
13111315
'instance : ID parameterlist ID LPAREN instance_ports RPAREN SEMICOLON'
13121316
p[0] = Instance(p[1], p[3], p[5], p[2])
13131317

1318+
def p_instance_or(self, p):
1319+
'instance : SENS_OR parameterlist ID LPAREN instance_ports RPAREN SEMICOLON'
1320+
p[0] = Instance(p[1], p[3], p[5], p[2])
1321+
13141322
def p_parameterlist(self, p):
13151323
'parameterlist : DELAY LPAREN param_args RPAREN'
13161324
p[0] = p[3]

0 commit comments

Comments
 (0)