branchign logic updated

Author: MostlyKIGuess

pipelined/modules/id_ex_register.v

@@ -4,13 +4,13 @@ module id_ex_register (
     input wire clk,
     input wire reset,
     input wire en,
-    input wire [230:0] d,
-    output reg [230:0] q
+    input wire [295:0] d,
+    output reg [295:0] q
 );
 
     always @(posedge clk or posedge reset) begin
         if (reset)
-            q <= {231{1'b0}};
+            q <= {296{1'b0}};
         else if (en)
             q <= d;
     end

pipelined/modules/if_id_register.v

@@ -4,13 +4,13 @@ module if_id_register (
     input wire clk,
     input wire reset,
     input wire en,
-    input wire [96:0] d,
-    output reg [96:0] q
+    input wire [161:0] d,
+    output reg [161:0] q
 );
 
     always @(posedge clk or posedge reset) begin
         if (reset)
-            q <= {97{1'b0}};
+            q <= {162{1'b0}};
         else if (en)
             q <= d;
     end

pipelined/testcases/6.s

@@ -1,12 +1,8 @@
-begin:
-    addi x1, x0, 10
-    addi x2, x1, 5
-    addi x3, x1, 20
-    add x4, x2, x3
-    addi x5, x4, 5
-    addi x6, x0, 100
-    sub x7, x5, x6
-    nop
+begin:  
+    addi x1, x0, 5
+    addi x2, x1, 1
+    add x3, x0, x1
+    addi x4, x1, 1 
+
 end:
-    nop
-    
+    nop

pipelined/testcases/7.s

@@ -3,6 +3,7 @@ begin:
     addi x7, x0, 4
     addi x8, x0, 5
     addi x9, x0, 6
+    addi x10, x0 , 10
 
 L1:
     addi x5, x0, 4