improved handling on branching

Author: MostlyKIGuess

pipelined/modules/register_file.v

@@ -13,7 +13,7 @@ module register_file(
     assign read_data1 = (rs1 == 0) ? 64'b0 : registers[rs1];
     assign read_data2 = (rs2 == 0) ? 64'b0 : registers[rs2];
 
-    always @(*) begin
+    always @(posedge clk) begin
         if (reg_write && rd != 0)
             registers[rd] <= write_data;
     end

pipelined/testcases/6.s

@@ -0,0 +1,12 @@
+begin:
+    addi x1, x0, 10
+    addi x2, x1, 5
+    addi x3, x1, 20
+    add x4, x2, x3
+    addi x5, x4, 5
+    addi x6, x0, 100
+    sub x7, x5, x6
+    nop
+end:
+    nop
+    

pipelined/testcases/7.s

@@ -0,0 +1,12 @@
+begin:
+    beq x0, x0, L1
+    addi x7, x0, 4
+    addi x8, x0, 5
+    addi x9, x0, 6
+
+L1:
+    addi x5, x0, 4
+    addi x6, x0, 5
+
+end:
+    nop

pipelined/testcases/assembler.py

@@ -327,7 +327,7 @@ def generate_testbench(instructions):
 
             // Show ID stage activity
             $display("ID Stage: rs1=x%0d (%0d), rs2=x%0d (%0d), rd=x%0d", 
-                cpu.rs1, cpu.reg_read_data1, cpu.rs2, cpu.reg_read_data2, cpu.rd);
+                cpu.rs1, cpu.reg_read_data1, cpu.rs2, cpu.reg_read_data2, cpu.reg_rd);
             
             // Show EX stage activity (removed alu_control as it doesn't exist)
             $display("EX Stage: ALU Result=%0h", cpu.alu_result);
@@ -341,9 +341,9 @@ def generate_testbench(instructions):
                     cpu.alu_result, cpu.mem_read_data);
                 
             // Show WB stage activity
-            if (cpu.reg_write && cpu.rd != 0)
+            if (cpu.reg_write && cpu.reg_rd != 0)
                 $display("WB Stage: Writing %0d to register x%0d", 
-                    cpu.reg_write_data, cpu.rd);
+                    cpu.reg_write_data, cpu.reg_rd);
             
             // Control signals
             $display("Control signals: branch=%b, mem_read=%b, mem_to_reg=%b, mem_write=%b, alu_src=%b, reg_write=%b",