added signal for end of program, BUG TO FIX: 1.s output sets all the registers except x1

Author: wig-nesh

pipelined/modules/ex_mem_register.v

@@ -4,13 +4,13 @@ module ex_mem_register (
     input wire clk,
     input wire reset,
     input wire en,
-    input wire [95:0] d,
-    output reg [95:0] q
+    input wire [294:0] d,
+    output reg [294:0] q
 );
 
     always @(posedge clk or posedge reset) begin
         if (reset)
-            q <= {96{1'b0}};
+            q <= {295{1'b0}};
         else if (en)
             q <= d;
     end

pipelined/modules/id_ex_register.v

@@ -4,13 +4,13 @@ module id_ex_register (
     input wire clk,
     input wire reset,
     input wire en,
-    input wire [229:0] d,
-    output reg [229:0] q
+    input wire [230:0] d,
+    output reg [230:0] q
 );
 
     always @(posedge clk or posedge reset) begin
         if (reset)
-            q <= {230{1'b0}};
+            q <= {231{1'b0}};
         else if (en)
             q <= d;
     end

pipelined/modules/if_id_register.v

@@ -4,13 +4,13 @@ module if_id_register (
     input wire clk,
     input wire reset,
     input wire en,
-    input wire [95:0] d,
-    output reg [95:0] q
+    input wire [96:0] d,
+    output reg [96:0] q
 );
 
     always @(posedge clk or posedge reset) begin
         if (reset)
-            q <= {96{1'b0}};
+            q <= {97{1'b0}};
         else if (en)
             q <= d;
     end

pipelined/modules/mem_wb_register.v

@@ -4,13 +4,13 @@ module mem_wb_register (
     input wire clk,
     input wire reset,
     input wire en,
-    input wire [161:0] d,
-    output reg [161:0] q
+    input wire [162:0] d,
+    output reg [162:0] q
 );
 
     always @(posedge clk or posedge reset) begin
         if (reset)
-            q <= {162{1'b0}};
+            q <= {163{1'b0}};
         else if (en)
             q <= d;
     end

pipelined/testcases/1.s

@@ -1,5 +1,9 @@
 begin:
-    addi x1, x0, 3
+    addi x1, x0, 1
+    addi x2, x0, 2
+    addi x3, x0, 3
+    addi x4, x0, 4
+    addi x5, x0, 5 
 
 exit:
     nop

pipelined/testcases/assembler.py

@@ -213,6 +213,8 @@ def generate_testbench(instructions):
 module testbench_pipelined();
     reg clk;
     reg reset;
+    wire end_program;
+
 
     integer cycle_count = 0;
     real execution_time;
@@ -227,12 +229,13 @@ def generate_testbench(instructions):
     
     initial begin
         reset = 1;
-        #15 reset = 0;
+        #6 reset = 0;
     end
     
     cpu_pipelined cpu(
         .clk(clk),
-        .reset(reset)
+        .reset(reset),
+        .end_program(end_program)
     );
     
     initial begin
@@ -247,10 +250,8 @@ def generate_testbench(instructions):
         
         @(negedge reset);
 
-        #15;
-
-        // Run simulation until a NOP (halt)
-        while (cpu.instruction !== 32'b0) begin
+        // Run simulation until end_program is high
+        while (!end_program) begin
             @(posedge clk);
         end
 

pipelined/verilog/cpu_pipelined.v

@@ -13,7 +13,8 @@
 
 module cpu_pipelined(
     input clk,                  
-    input reset                 
+    input reset,
+    output end_program           
 );
     // program counter wale baba
     wire [63:0] pc_next;        
@@ -35,17 +36,21 @@ module cpu_pipelined(
         .pc(pc_current),         // current PC se
         .instruction(instruction) // instruction nikalo
     );
+
+    wire nop_instruction;
+    assign nop_instruction = instruction == 0;  // no operation instruction
 
     // IF/ID Pipeline Register
     wire [63:0] if_id_pc;
     wire [31:0] if_id_instruction;
+    wire if_id_end_instruction, if_id_nop_instruction;
 
     if_id_register if_id(
         .clk(clk),
         .reset(reset),
         .en(1'b1),
-        .d({pc_current, instruction}),
-        .q({  if_id_pc, if_id_instruction})
+        .d({pc_current, instruction      , nop_instruction}),
+        .q({if_id_pc  , if_id_instruction, if_id_nop_instruction})
     );
 
     // control signals - CPU ko batate hai kya karna hai
@@ -94,14 +99,14 @@ module cpu_pipelined(
     // ID/EX Pipeline Register
     wire [63:0] id_ex_pc, id_ex_reg_read_data1, id_ex_reg_read_data2;
     wire [31:0] id_ex_instruction;
-    wire id_ex_branch, id_ex_mem_read, id_ex_mem_write, id_ex_mem_to_reg, id_ex_reg_write, id_ex_alu_src;
+    wire id_ex_branch, id_ex_mem_read, id_ex_mem_write, id_ex_mem_to_reg, id_ex_reg_write, id_ex_alu_src, id_ex_nop_instruction;
 
     id_ex_register id_ex(
         .clk(clk),
         .reset(reset),
         .en(1'b1),
-        .d({if_id_pc,       reg_read_data1,       reg_read_data2, if_id_instruction,       branch,       mem_read,       mem_write,       mem_to_reg,       reg_write,       alu_src}),
-        .q({id_ex_pc, id_ex_reg_read_data1, id_ex_reg_read_data2, id_ex_instruction, id_ex_branch, id_ex_mem_read, id_ex_mem_write, id_ex_mem_to_reg, id_ex_reg_write, id_ex_alu_src})
+        .d({if_id_pc,       reg_read_data1,       reg_read_data2, if_id_instruction,       branch,       mem_read,       mem_write,       mem_to_reg,       reg_write,       alu_src, if_id_nop_instruction}),
+        .q({id_ex_pc, id_ex_reg_read_data1, id_ex_reg_read_data2, id_ex_instruction, id_ex_branch, id_ex_mem_read, id_ex_mem_write, id_ex_mem_to_reg, id_ex_reg_write, id_ex_alu_src, id_ex_nop_instruction})
     );
 
     // ALU ke signals
@@ -132,14 +137,14 @@ module cpu_pipelined(
     // EX/MEM Pipeline Register
     wire [63:0] ex_mem_pc, ex_mem_alu_result, ex_mem_reg_read_data2, ex_mem_branch_target;
     wire [31:0] ex_mem_instruction;
-    wire ex_mem_zero, ex_mem_branch, ex_mem_mem_read, ex_mem_mem_write, ex_mem_mem_to_reg, ex_mem_reg_write;
+    wire ex_mem_zero, ex_mem_branch, ex_mem_mem_read, ex_mem_mem_write, ex_mem_mem_to_reg, ex_mem_reg_write, ex_mem_nop_instruction;
 
     ex_mem_register ex_mem(
         .clk(clk),
         .reset(reset),
         .en(1'b1),
-        .d({id_ex_pc , alu_result       , id_ex_reg_read_data2 , branch_target       , id_ex_instruction , zero       , id_ex_branch , id_ex_mem_read , id_ex_mem_write , id_ex_mem_to_reg , id_ex_reg_write}),
-        .q({ex_mem_pc, ex_mem_alu_result, ex_mem_reg_read_data2, ex_mem_branch_target, ex_mem_instruction, ex_mem_zero, ex_mem_branch, ex_mem_mem_read, ex_mem_mem_write, ex_mem_mem_to_reg, ex_mem_reg_write})
+        .d({id_ex_pc , alu_result       , id_ex_reg_read_data2 , branch_target       , id_ex_instruction , zero       , id_ex_branch , id_ex_mem_read , id_ex_mem_write , id_ex_mem_to_reg , id_ex_reg_write , id_ex_nop_instruction}),
+        .q({ex_mem_pc, ex_mem_alu_result, ex_mem_reg_read_data2, ex_mem_branch_target, ex_mem_instruction, ex_mem_zero, ex_mem_branch, ex_mem_mem_read, ex_mem_mem_write, ex_mem_mem_to_reg, ex_mem_reg_write, ex_mem_nop_instruction})
     );
 
     wire branch_taken;          // jump karna hai ya nahi
@@ -163,19 +168,22 @@ module cpu_pipelined(
     // MEM/WB Pipeline Register
     wire [63:0] mem_wb_mem_read_data, mem_wb_alu_result;
     wire [31:0] mem_wb_instruction;
-    wire mem_wb_mem_to_reg, mem_wb_reg_write;
+    wire mem_wb_mem_to_reg, mem_wb_reg_write, mem_wb_nop_instruction;
 
     mem_wb_register mem_wb(
         .clk(clk),
         .reset(reset),
         .en(1'b1),
-        .d({mem_read_data       , ex_mem_alu_result, ex_mem_instruction, ex_mem_mem_to_reg, ex_mem_reg_write}),
-        .q({mem_wb_mem_read_data, mem_wb_alu_result, mem_wb_instruction, mem_wb_mem_to_reg, mem_wb_reg_write})
+        .d({mem_read_data       , ex_mem_alu_result, ex_mem_instruction, ex_mem_mem_to_reg, ex_mem_reg_write, ex_mem_nop_instruction}),
+        .q({mem_wb_mem_read_data, mem_wb_alu_result, mem_wb_instruction, mem_wb_mem_to_reg, mem_wb_reg_write, mem_wb_nop_instruction})
     );
 
 
     // register me value write back karo
     assign reg_write_data = mem_wb_mem_to_reg ? mem_wb_mem_read_data : mem_wb_alu_result;  // memory se ya ALU se value select karo
     assign rd = mem_wb_instruction[11:7];  // destination register ka number
 
+    // end_program signal
+    assign end_program = mem_wb_nop_instruction;
+
 endmodule

pipelined/verilog/testbench_pipelined.v

@@ -3,6 +3,8 @@
 module testbench_pipelined();
     reg clk;
     reg reset;
+    wire end_program;
+
 
     integer cycle_count = 0;
     real execution_time;
@@ -17,17 +19,22 @@ module testbench_pipelined();
 
     initial begin
         reset = 1;
-        #15 reset = 0;
+        #6 reset = 0;
     end
 
     cpu_pipelined cpu(
         .clk(clk),
-        .reset(reset)
+        .reset(reset),
+        .end_program(end_program)
     );
 
     initial begin
-        cpu.imem.memory[0] = 32'b00000000001100000000000010010011;
-        cpu.imem.memory[1] = 32'b00000000000000000000000000000000;
+        cpu.imem.memory[0] = 32'b00000000000100000000000010010011;
+        cpu.imem.memory[1] = 32'b00000000001000000000000100010011;
+        cpu.imem.memory[2] = 32'b00000000001100000000000110010011;
+        cpu.imem.memory[3] = 32'b00000000010000000000001000010011;
+        cpu.imem.memory[4] = 32'b00000000010100000000001010010011;
+        cpu.imem.memory[5] = 32'b00000000000000000000000000000000;
     end
 
 
@@ -38,10 +45,8 @@ module testbench_pipelined();
 
         @(negedge reset);
 
-        #15;
-
-        // Run simulation until a NOP (halt)
-        while (cpu.instruction !== 32'b0) begin
+        // Run simulation until end_program is high
+        while (!end_program) begin
             @(posedge clk);
         end