split registers into modules

Author: wig-nesh

pipelined/modules/ex_mem_register.v

@@ -0,0 +1,18 @@
+`timescale 1ns/1ps
+
+module ex_mem_register (
+    input wire clk,
+    input wire reset,
+    input wire en,
+    input wire [95:0] d,
+    output reg [95:0] q
+);
+
+    always @(posedge clk or posedge reset) begin
+        if (reset)
+            q <= {96{1'b0}};
+        else if (en)
+            q <= d;
+    end
+    
+endmodule

pipelined/modules/param_register.v renamed to pipelined/modules/id_ex_register.v

@@ -1,16 +1,16 @@
 `timescale 1ns/1ps
 
-module param_register #(parameter WIDTH = 1) (
+module id_ex_register (
     input wire clk,
     input wire reset,
     input wire en,
-    input wire [WIDTH-1:0] d,
-    output reg [WIDTH-1:0] q
+    input wire [229:0] d,
+    output reg [229:0] q
 );
 
     always @(posedge clk or posedge reset) begin
         if (reset)
-            q <= {WIDTH{1'b0}};
+            q <= {230{1'b0}};
         else if (en)
             q <= d;
     end

pipelined/modules/if_id_register.v

@@ -0,0 +1,18 @@
+`timescale 1ns/1ps
+
+module if_id_register (
+    input wire clk,
+    input wire reset,
+    input wire en,
+    input wire [95:0] d,
+    output reg [95:0] q
+);
+    
+    always @(posedge clk or posedge reset) begin
+        if (reset)
+            q <= {96{1'b0}};
+        else if (en)
+            q <= d;
+    end
+    
+endmodule

pipelined/modules/mem_wb_register.v

@@ -0,0 +1,18 @@
+`timescale 1ns/1ps
+
+module mem_wb_register (
+    input wire clk,
+    input wire reset,
+    input wire en,
+    input wire [161:0] d,
+    output reg [161:0] q
+);
+
+    always @(posedge clk or posedge reset) begin
+        if (reset)
+            q <= {162{1'b0}};
+        else if (en)
+            q <= d;
+    end
+    
+endmodule

pipelined/testcases/assembler.py

@@ -227,7 +227,7 @@ def generate_testbench(instructions):
     
     initial begin
         reset = 1;
-        #5 reset = 0;
+        #15 reset = 0;
     end
     
     cpu_pipelined cpu(

pipelined/verilog/cpu_pipelined.v

@@ -6,7 +6,10 @@
 `include "modules/register_file.v"
 `include "modules/data_memory.v"
 `include "modules/control_unit.v"
-`include "modules/param_register.v"
+`include "modules/if_id_register.v"
+`include "modules/id_ex_register.v"
+`include "modules/ex_mem_register.v"
+`include "modules/mem_wb_register.v"
 
 module cpu_pipelined(
     input clk,                  
@@ -37,10 +40,11 @@ module cpu_pipelined(
     wire [63:0] if_id_pc;
     wire [31:0] if_id_instruction;
 
-    param_register #(96) if_id(
+    if_id_register if_id(
         .clk(clk),
         .reset(reset),
-        .d({pc_current,       instruction}),
+        .en(1'b1),
+        .d({pc_current, instruction}),
         .q({  if_id_pc, if_id_instruction})
     );
 
@@ -92,9 +96,10 @@ module cpu_pipelined(
     wire [31:0] id_ex_instruction;
     wire id_ex_branch, id_ex_mem_read, id_ex_mem_write, id_ex_mem_to_reg, id_ex_reg_write, id_ex_alu_src;
 
-    param_register #(230) id_ex(
+    id_ex_register id_ex(
         .clk(clk),
         .reset(reset),
+        .en(1'b1),
         .d({if_id_pc,       reg_read_data1,       reg_read_data2, if_id_instruction,       branch,       mem_read,       mem_write,       mem_to_reg,       reg_write,       alu_src}),
         .q({id_ex_pc, id_ex_reg_read_data1, id_ex_reg_read_data2, id_ex_instruction, id_ex_branch, id_ex_mem_read, id_ex_mem_write, id_ex_mem_to_reg, id_ex_reg_write, id_ex_alu_src})
     );
@@ -129,9 +134,10 @@ module cpu_pipelined(
     wire [31:0] ex_mem_instruction;
     wire ex_mem_zero, ex_mem_branch, ex_mem_mem_read, ex_mem_mem_write, ex_mem_mem_to_reg, ex_mem_reg_write;
 
-    param_register #(294) ex_mem(
+    ex_mem_register ex_mem(
         .clk(clk),
         .reset(reset),
+        .en(1'b1),
         .d({id_ex_pc , alu_result       , id_ex_reg_read_data2 , branch_target       , id_ex_instruction , zero       , id_ex_branch , id_ex_mem_read , id_ex_mem_write , id_ex_mem_to_reg , id_ex_reg_write}),
         .q({ex_mem_pc, ex_mem_alu_result, ex_mem_reg_read_data2, ex_mem_branch_target, ex_mem_instruction, ex_mem_zero, ex_mem_branch, ex_mem_mem_read, ex_mem_mem_write, ex_mem_mem_to_reg, ex_mem_reg_write})
     );
@@ -159,9 +165,10 @@ module cpu_pipelined(
     wire [31:0] mem_wb_instruction;
     wire mem_wb_mem_to_reg, mem_wb_reg_write;
 
-    param_register #(162) mem_wb(
+    mem_wb_register mem_wb(
         .clk(clk),
         .reset(reset),
+        .en(1'b1),
         .d({mem_read_data       , ex_mem_alu_result, ex_mem_instruction, ex_mem_mem_to_reg, ex_mem_reg_write}),
         .q({mem_wb_mem_read_data, mem_wb_alu_result, mem_wb_instruction, mem_wb_mem_to_reg, mem_wb_reg_write})
     );

pipelined/verilog/testbench_pipelined.v

@@ -17,7 +17,7 @@ module testbench_pipelined();
 
     initial begin
         reset = 1;
-        #5 reset = 0;
+        #15 reset = 0;
     end
 
     cpu_pipelined cpu(

sequential/verilog/testbench_sequential.v

@@ -26,12 +26,13 @@ module testbench_sequential();
     );
 
     initial begin
-        cpu.imem.memory[0] = 32'b00000000101000000000001100010011;
-        cpu.imem.memory[1] = 32'b00000000000000000000001110010011;
-        cpu.imem.memory[2] = 32'b01000000000000000000010000010011;
-        cpu.imem.memory[3] = 32'b00000000011000111010000000100011;
-        cpu.imem.memory[4] = 32'b00000000011001000010000000100011;
-        cpu.imem.memory[5] = 32'b00000000000000000000000000000000;
+        cpu.imem.memory[0] = 32'b00000000001100000000000010010011;
+        cpu.imem.memory[1] = 32'b00000000011100000000000100010011;
+        cpu.imem.memory[2] = 32'b00000000000000001000100001100011;
+        cpu.imem.memory[3] = 32'b00000000000100010000000100110011;
+        cpu.imem.memory[4] = 32'b11111111111100001000000010010011;
+        cpu.imem.memory[5] = 32'b11111110000000000000101011100011;
+        cpu.imem.memory[6] = 32'b00000000000000000000000000000000;
     end
 
 

sequential/visualization/cpu-data.js

@@ -3,8 +3,8 @@ const cpuData = {
     {
       "time": 15000,
       "pc": 0,
-      "instruction": 10486547,
-      "decodedInstruction": "addi x6, x0, 10",
+      "instruction": 3145875,
+      "decodedInstruction": "addi x1, x0, 3",
       "controlSignals": {
         "branch": false,
         "mem_read": false,
@@ -15,12 +15,12 @@ const cpuData = {
       },
       "registers": [
         0,
+        3,
         0,
         0,
         0,
         0,
         0,
-        10,
         0,
         0,
         0,
@@ -48,7 +48,7 @@ const cpuData = {
         0
       ],
       "changedRegisters": [
-        6
+        1
       ],
       "memory": [
         0,
@@ -308,13 +308,13 @@ const cpuData = {
         0,
         0
       ],
-      "aluResult": 10
+      "aluResult": 3
     },
     {
       "time": 25000,
       "pc": 4,
-      "instruction": 915,
-      "decodedInstruction": "addi x7, x0, 0",
+      "instruction": 7340307,
+      "decodedInstruction": "addi x2, x0, 7",
       "controlSignals": {
         "branch": false,
         "mem_read": false,
@@ -325,13 +325,13 @@ const cpuData = {
       },
       "registers": [
         0,
+        3,
+        7,
         0,
         0,
         0,
         0,
         0,
-        10,
-        0,
         0,
         0,
         0,
@@ -358,7 +358,7 @@ const cpuData = {
         0
       ],
       "changedRegisters": [
-        7
+        2
       ],
       "memory": [
         0,
@@ -618,7 +618,7 @@ const cpuData = {
         0,
         0
       ],
-      "aluResult": 0
+      "aluResult": 7
     }
   ]
 };