fixed data_memory in sequential

Author: wig-nesh

pipelined/modules/program_counter.v

@@ -2,12 +2,13 @@ module program_counter(
     input clk,
     input reset,
     input [63:0] next_pc,
+    input stall,
     output reg [63:0] pc
 );
     always @(posedge clk or posedge reset) begin
         if (reset)
             pc <= 64'b0;
-        else
+        else if (!stall)
             pc <= next_pc;
     end
 endmodule

pipelined/test_pipelined.sh

@@ -29,7 +29,7 @@ if [ $? -eq 0 ]; then
     # if you wanna generate waveforms bruhhhh
     if [ -f test_results/cpu_pipelined_test.vcd ]; then
         echo "Generating waveform..."
-        gtkwave test_results/cpu_pipelined_test.vcd &
+        gtkwave -A --rcvar 'fontname_signals Monospace 12' --rcvar 'fontname_waves Monospace 12' test_results/cpu_pipelined_test.vcd &
     else
         echo "Error: Waveform file not generated"
     fi

pipelined/testcases/3.s

@@ -1,9 +1,15 @@
 begin:
     beq x0, x0, L1
-    addi x6, x0, 3
+    addi x6, x0, 4
+
+L2:
+    addi x7, x0, 8
 
 L1:
     addi x5, x0, 4
 
 end:
-    nop
+    nop
+
+
+# only x5

pipelined/testcases/4.s

@@ -1,14 +1,15 @@
 begin:
-    beq x0, x0, end
+    addi x4, x0, 1
+    addi x8, x0, 1
+    addi x8, x0, 1
+    beq x0, x4, L1
+    addi x6, x0, 4
 
 L1:
     addi x5, x0, 4
 
-L2:
-    addi x6, x0, 4
+end:
+    nop
 
-L3:
-    addi x7, x0, 4
 
-end:
-    nop
+# both x5 and x6

pipelined/testcases/assembler.py

@@ -67,8 +67,8 @@ def main():
 
             # Handle NOP instruction
             if tokens[0] == "nop":
-                # NOP is encoded as all zeros
-                binary_instruction = "00000000000000000000000000000000"
+                # NOP is encoded as all ones
+                binary_instruction = "11111111111111111111111111111111"
                 instructions.append(f"        cpu.imem.memory[{instruction_index}] = 32'b{binary_instruction};")
                 current_address += 4
                 instruction_index += 1
@@ -231,7 +231,7 @@ def generate_testbench(instructions):
         // promper initialization
         #10 reset = 0;
         
-        forever #5 clk = ~clk; 
+        forever #15 clk = ~clk; 
     end
     
     cpu_pipelined cpu(

pipelined/verilog/cpu_pipelined.v

@@ -28,34 +28,36 @@ module cpu_pipelined(
         .clk(clk),
         .reset(reset),
         .next_pc(pc_next),      // agli instruction ka address
+        .stall(branch_stall),
         .pc(pc_current)         // current instruction ka address
     );
 
+
     // program instructions ko store karta hai
     instruction_memory imem( // REMEMBER INITIALIZED AS imem, so you can do cpu.imem.memory[0] in testbench
         .pc(pc_current),         // current PC se
         .instruction(instruction) // instruction nikalo
     );
 
     wire nop_instruction;
-    assign nop_instruction = instruction == 0;  // no operation instruction
+    assign nop_instruction = instruction == -1;  // no operation instruction
 
     // IF/ID Pipeline Register
     wire [63:0] if_id_pc;
     wire [31:0] if_id_instruction;
     wire if_id_end_instruction, if_id_nop_instruction;
 
     // check if_id_instruction to see if it is beq(opcode 1100011), send addi x0 x0 0, also sent pc_next = pc_current
-    wire branch_halt;
-    assign branch_halt = if_id_instruction[6:0] == 7'b1100011;
-    wire [31:0] halt_instruction;
-    assign halt_instruction = branch_halt ? 32'b00000000000000000000000000010011 : instruction;
+    wire branch_stall;
+    assign branch_stall = if_id_instruction[6:0] == 7'b1100011;
+    wire [31:0] stall_instruction;
+    assign stall_instruction = branch_stall ? 32'b00000000000000000000000000000000 : instruction;
 
     if_id_register if_id(
         .clk(clk),
         .reset(reset),
         .en(1'b1),
-        .d({pc_current, halt_instruction , nop_instruction}),
+        .d({pc_current, stall_instruction, nop_instruction}),
         .q({if_id_pc  , if_id_instruction, if_id_nop_instruction})
     );
 
@@ -154,8 +156,10 @@ module cpu_pipelined(
     );
 
     wire branch_taken;          // jump karna hai ya nahi
-    assign branch_taken = ex_mem_branch & ex_mem_zero;                    // branch lena hai ya nahi
-    assign pc_next = branch_taken ? ex_mem_branch_target : (branch_halt? pc_current : pc_current + 4);                       // next PC set karo
+    assign branch_taken = id_ex_branch & zero;                            // branch lena hai ya nahi
+    assign pc_next = branch_taken ? branch_target : id_ex_pc + 4;         // next PC set karo
+    // assign branch_taken = ex_mem_branch & ex_mem_zero;                    // branch lena hai ya nahi
+    // assign pc_next = branch_taken ? ex_mem_branch_target : ex_mem_pc + 4; // next PC set karo
 
     // memory ke signals
     wire signed [63:0] mem_read_data;  // memory se padhi hui value

pipelined/verilog/testbench_pipelined.v

@@ -16,16 +16,16 @@ module testbench_pipelined();
         reset = 1;
 
         // Initialize instruction memory first
-        cpu.imem.memory[0] = 32'b00000000000000000000100001100011;
-        cpu.imem.memory[1] = 32'b00000000010000000000001010010011;
-        cpu.imem.memory[2] = 32'b00000000010000000000001100010011;
-        cpu.imem.memory[3] = 32'b00000000010000000000001110010011;
-        cpu.imem.memory[4] = 32'b00000000000000000000000000000000;
+        cpu.imem.memory[0] = 32'b00000000000000000000011001100011;
+        cpu.imem.memory[1] = 32'b00000000010000000000001100010011;
+        cpu.imem.memory[2] = 32'b00000000100000000000001110010011;
+        cpu.imem.memory[3] = 32'b00000000010000000000001010010011;
+        cpu.imem.memory[4] = 32'b11111111111111111111111111111111;
 
         // promper initialization
         #10 reset = 0;
 
-        forever #5 clk = ~clk; 
+        forever #15 clk = ~clk; 
     end
 
     cpu_pipelined cpu(

sequential/modules/data_memory.v

@@ -15,7 +15,7 @@ module data_memory(
     end
 
     always @(posedge clk) begin
-        if (address > 1016) begin
+        if (address > 1016 && mem_write) begin
             $fatal(1, "\n\nError: Invalid memory address %d\n", address);
         end
         if (mem_write && address <= 1016) begin
@@ -31,7 +31,7 @@ module data_memory(
     end
 
     always @(*) begin
-        if (address > 1016) begin
+        if (address > 1016 && mem_read) begin
             $fatal(1, "\n\nError: Invalid memory address %d\n", address);
         end
         if (mem_read && address <= 1016) begin

sequential/testcases/8.s

@@ -1,14 +1,15 @@
 begin:
-    beq x0, x0, end
+    beq x0, x0, L1
+    addi x6, x0, 4
+
+L2:
+    addi x7, x0, 8
 
 L1:
     addi x5, x0, 4
 
-L2:
-    addi x6, x0, 4
+end:
+    nop
 
-L3:
-    addi x7, x0, 4
 
-end:
-    nop
+# only x5

sequential/verilog/testbench_sequential.v

@@ -1,4 +1,4 @@
-nb`timescale 1ns/1ps
+`timescale 1ns/1ps
 
 module testbench_sequential();
     reg clk;
@@ -26,10 +26,10 @@ module testbench_sequential();
     );
 
     initial begin
-        cpu.imem.memory[0] = 32'b00000000000000000000100001100011;
-        cpu.imem.memory[1] = 32'b00000000010000000000001010010011;
-        cpu.imem.memory[2] = 32'b00000000010000000000001100010011;
-        cpu.imem.memory[3] = 32'b00000000010000000000001110010011;
+        cpu.imem.memory[0] = 32'b00000000000000000000011001100011;
+        cpu.imem.memory[1] = 32'b00000000010000000000001100010011;
+        cpu.imem.memory[2] = 32'b00000000100000000000001110010011;
+        cpu.imem.memory[3] = 32'b00000000010000000000001010010011;
         cpu.imem.memory[4] = 32'b00000000000000000000000000000000;
     end