fixed data_memory in sequential

Author: wig-nesh

sequential/modules/data_memory.v

@@ -15,7 +15,7 @@ module data_memory(
     end
 
     always @(posedge clk) begin
-        if (address > 1016) begin
+        if (address > 1016 && mem_write) begin
             $fatal(1, "\n\nError: Invalid memory address %d\n", address);
         end
         if (mem_write && address <= 1016) begin
@@ -31,7 +31,7 @@ module data_memory(
     end
 
     always @(*) begin
-        if (address > 1016) begin
+        if (address > 1016 && mem_read) begin
             $fatal(1, "\n\nError: Invalid memory address %d\n", address);
         end
         if (mem_read && address <= 1016) begin

sequential/testcases/8.s

@@ -1,14 +1,15 @@
 begin:
-    beq x0, x0, end
+    beq x0, x0, L1
+    addi x6, x0, 4
+
+L2:
+    addi x7, x0, 8
 
 L1:
     addi x5, x0, 4
 
-L2:
-    addi x6, x0, 4
+end:
+    nop
 
-L3:
-    addi x7, x0, 4
 
-end:
-    nop
+# only x5

sequential/verilog/testbench_sequential.v

@@ -1,4 +1,4 @@
-nb`timescale 1ns/1ps
+`timescale 1ns/1ps
 
 module testbench_sequential();
     reg clk;
@@ -26,10 +26,10 @@ module testbench_sequential();
     );
 
     initial begin
-        cpu.imem.memory[0] = 32'b00000000000000000000100001100011;
-        cpu.imem.memory[1] = 32'b00000000010000000000001010010011;
-        cpu.imem.memory[2] = 32'b00000000010000000000001100010011;
-        cpu.imem.memory[3] = 32'b00000000010000000000001110010011;
+        cpu.imem.memory[0] = 32'b00000000000000000000011001100011;
+        cpu.imem.memory[1] = 32'b00000000010000000000001100010011;
+        cpu.imem.memory[2] = 32'b00000000100000000000001110010011;
+        cpu.imem.memory[3] = 32'b00000000010000000000001010010011;
         cpu.imem.memory[4] = 32'b00000000000000000000000000000000;
     end