Branch halting works: hrishikesh

Author: wig-nesh

.gitignore

@@ -1,2 +1,4 @@
 pipelined/test_results/
-sequential/test_results/
+sequential/test_results/
+test.c
+./a.out

a.out

@@ -1,5 +1,6 @@
 begin:
     addi x1, x0, 1
     addi x2, x0, 2
+    
 exit:
     nop

pipelined/testcases/1.s

@@ -0,0 +1,12 @@
+begin:
+    addi x1, x0, 3      # x1 = 3
+    addi x2, x0, 7      # x2 = 7
+
+loop:
+    beq x1, x0, exit    # if x1==0, end program
+    add x2, x2, x1      # x2 = x1 + x2
+    addi x1, x1, -1     # x1--
+    beq x0, x0, loop    # loop
+
+exit:
+    nop

pipelined/testcases/2.s

@@ -0,0 +1,12 @@
+begin:
+    addi x4, x5, 1
+    addi x8, x0, 0
+    addi x8, x0, 0
+    beq x1, x4, L1
+    addi x6, x0, 3
+
+L1:
+    addi x5, x0, 4
+
+end:
+    nop

pipelined/testcases/3.s

@@ -45,14 +45,21 @@ module cpu_pipelined(
     wire [31:0] if_id_instruction;
     wire if_id_end_instruction, if_id_nop_instruction;
 
+    // check if_id_instruction to see if it is beq(opcode 1100011), send addi x0 x0 0, also sent pc_next = pc_current
+    wire branch_halt;
+    assign branch_halt = if_id_instruction[6:0] == 7'b1100011;
+    wire [31:0] halt_instruction;
+    assign halt_instruction = branch_halt ? 32'b00000000000000000000000000010011 : instruction;
+
     if_id_register if_id(
         .clk(clk),
         .reset(reset),
         .en(1'b1),
-        .d({pc_current, instruction      , nop_instruction}),
+        .d({pc_current, halt_instruction , nop_instruction}),
         .q({if_id_pc  , if_id_instruction, if_id_nop_instruction})
     );
 
+
     // control signals - CPU ko batate hai kya karna hai
     wire branch;                // branch instruction hai ya nahi
     wire mem_read;              // memory se padhna hai
@@ -82,7 +89,6 @@ module cpu_pipelined(
     // Register File ke inputs set karo
     assign rs1 = if_id_instruction[19:15];  // source register 1 ka number
     assign rs2 = if_id_instruction[24:20];  // source register 2 ka number
-    // assign rd = if_id_instruction[11:7];    // destination register ka number
 
     // Register File - CPU ke registers ko handle karta hai
     register_file reg_file(
@@ -149,7 +155,7 @@ module cpu_pipelined(
 
     wire branch_taken;          // jump karna hai ya nahi
     assign branch_taken = ex_mem_branch & ex_mem_zero;                    // branch lena hai ya nahi
-    assign pc_next = branch_taken ? ex_mem_branch_target : pc_current + 4;                       // next PC set karo
+    assign pc_next = branch_taken ? ex_mem_branch_target : (branch_halt? pc_current : pc_current + 4);                       // next PC set karo
 
     // memory ke signals
     wire signed [63:0] mem_read_data;  // memory se padhi hui value

pipelined/verilog/cpu_pipelined.v

@@ -16,10 +16,17 @@ module testbench_pipelined();
         reset = 1;
 
         // Initialize instruction memory first
-        cpu.imem.memory[0] = 32'b00000000000100000000000010010011;
-        cpu.imem.memory[1] = 32'b00000000001000000000000100010011;
-        cpu.imem.memory[2] = 32'b00000000000000000000000000000000;
-    
+        cpu.imem.memory[0] = 32'b00000000000100101000001000010011;
+        cpu.imem.memory[1] = 32'b00000000000000000000010000010011;
+        cpu.imem.memory[2] = 32'b00000000000000000000010000010011;
+        cpu.imem.memory[3] = 32'b00000000010000001000010001100011;
+        cpu.imem.memory[4] = 32'b00000000001100000000001100010011;
+        cpu.imem.memory[5] = 32'b00000000010000000000001010010011;
+        cpu.imem.memory[6] = 32'b00000000000000000000000000000000;
+        
+        // promper initialization
+        #10 reset = 0;
+        
         forever #5 clk = ~clk; 
     end