Merge remote-tracking branch 'refs/remotes/origin/main'

Author: MostlyKIGuess

pipelined/modules/register_file.v

@@ -13,7 +13,7 @@ module register_file(
     assign read_data1 = (rs1 == 0) ? 64'b0 : registers[rs1];
     assign read_data2 = (rs2 == 0) ? 64'b0 : registers[rs2];
 
-    always @(posedge clk) begin
+    always @(*) begin
         if (reg_write && rd != 0)
             registers[rd] <= write_data;
     end

pipelined/testcases/1.s

@@ -1,9 +1,5 @@
 begin:
     addi x1, x0, 1
     addi x2, x0, 2
-    addi x3, x0, 3
-    addi x4, x0, 4
-    addi x5, x0, 5 
-
 exit:
     nop

pipelined/verilog/cpu_pipelined.v

@@ -82,16 +82,16 @@ module cpu_pipelined(
     // Register File ke inputs set karo
     assign rs1 = if_id_instruction[19:15];  // source register 1 ka number
     assign rs2 = if_id_instruction[24:20];  // source register 2 ka number
-    assign rd = if_id_instruction[11:7];    // destination register ka number
+    // assign rd = if_id_instruction[11:7];    // destination register ka number
 
     // Register File - CPU ke registers ko handle karta hai
     register_file reg_file(
         .clk(clk),
         .rs1(rs1),                    // pehla source register
         .rs2(rs2),                    // dusra source register
-        .rd(rd),                      // destination register
+        .rd(reg_rd),                      // destination register
         .write_data(reg_write_data),  // jo value likhni hai
-        .reg_write(reg_write),        // write enable signal
+        .reg_write(mem_wb_reg_write),        // write enable signal
         .read_data1(reg_read_data1),  // pehle register ki value
         .read_data2(reg_read_data2)   // dusre register ki value
     );
@@ -178,10 +178,11 @@ module cpu_pipelined(
         .q({mem_wb_mem_read_data, mem_wb_alu_result, mem_wb_instruction, mem_wb_mem_to_reg, mem_wb_reg_write, mem_wb_nop_instruction})
     );
 
+    wire [4:0] reg_rd;
 
     // register me value write back karo
     assign reg_write_data = mem_wb_mem_to_reg ? mem_wb_mem_read_data : mem_wb_alu_result;  // memory se ya ALU se value select karo
-    assign rd = mem_wb_instruction[11:7];  // destination register ka number
+    assign reg_rd = mem_wb_instruction[11:7];  // destination register ka number
 
     // end_program signal
     assign end_program = mem_wb_nop_instruction;

pipelined/verilog/testbench_pipelined.v

@@ -18,14 +18,8 @@ module testbench_pipelined();
         // Initialize instruction memory first
         cpu.imem.memory[0] = 32'b00000000000100000000000010010011;
         cpu.imem.memory[1] = 32'b00000000001000000000000100010011;
-        cpu.imem.memory[2] = 32'b00000000001100000000000110010011;
-        cpu.imem.memory[3] = 32'b00000000010000000000001000010011;
-        cpu.imem.memory[4] = 32'b00000000010100000000001010010011;
-        cpu.imem.memory[5] = 32'b00000000000000000000000000000000;
-        
-        // promper initialization
-        #10 reset = 0;
-        
+        cpu.imem.memory[2] = 32'b00000000000000000000000000000000;
+    
         forever #5 clk = ~clk; 
     end