1.s works, with a workaround

Author: wig-nesh

pipelined/testcases/1.s

@@ -1,4 +1,5 @@
 begin:
+    addi x0, x0, 1 # does nothing
     addi x1, x0, 1
     addi x2, x0, 2
     addi x3, x0, 3

pipelined/verilog/testbench_pipelined.v

@@ -29,12 +29,13 @@ module testbench_pipelined();
     );
 
     initial begin
-        cpu.imem.memory[0] = 32'b00000000000100000000000010010011;
-        cpu.imem.memory[1] = 32'b00000000001000000000000100010011;
-        cpu.imem.memory[2] = 32'b00000000001100000000000110010011;
-        cpu.imem.memory[3] = 32'b00000000010000000000001000010011;
-        cpu.imem.memory[4] = 32'b00000000010100000000001010010011;
-        cpu.imem.memory[5] = 32'b00000000000000000000000000000000;
+        cpu.imem.memory[0] = 32'b00000000000100000000000000010011;
+        cpu.imem.memory[1] = 32'b00000000000100000000000010010011;
+        cpu.imem.memory[2] = 32'b00000000001000000000000100010011;
+        cpu.imem.memory[3] = 32'b00000000001100000000000110010011;
+        cpu.imem.memory[4] = 32'b00000000010000000000001000010011;
+        cpu.imem.memory[5] = 32'b00000000010100000000001010010011;
+        cpu.imem.memory[6] = 32'b00000000000000000000000000000000;
     end