branch prediction works

Author: MostlyKIGuess

pipelined/verilog/cpu_pipelined.v

@@ -363,6 +363,6 @@ module cpu_pipelined(
     assign reg_rd = mem_wb_rd_fixed;
 
     // End of Program
-    assign end_program = mem_wb_nop_instruction;
+    assign end_program = mem_wb_nop_instruction & ~ branch_predicted;
 
 endmodule

pipelined/verilog/testbench_pipelined.v

@@ -16,10 +16,11 @@ module testbench_pipelined();
         reset = 1;
 
         // Initialize instruction memory first
-        cpu.imem.memory[0] = 32'b00000000000000000000010001100011;
-        cpu.imem.memory[1] = 32'b00000000001100000000001100010011;
-        cpu.imem.memory[2] = 32'b00000000010000000000001010010011;
-        cpu.imem.memory[3] = 32'b00000000000000000000000000000000;
+        cpu.imem.memory[0] = 32'b00000000000000000000100001100011;
+        cpu.imem.memory[1] = 32'b00000000010000000000001010010011;
+        cpu.imem.memory[2] = 32'b00000000010000000000001100010011;
+        cpu.imem.memory[3] = 32'b00000000010000000000001110010011;
+        cpu.imem.memory[4] = 32'b00000000000000000000000000000000;
 
         // promper initialization
         #10 reset = 0;