@@ -209,13 +209,13 @@ static void maple_vmu_block_write(maple_frame_t *req, maple_frame_t *resp) {
209209 LOGF (" BWRITE: device busy\n" );
210210 return ;
211211 }
212- uint16 block_size = STORAGE_FUNC_BLOCK_SIZE (device_info );
213- uint8 phase_count = STORAGE_FUNC_WRITE_PHASE_COUNT (device_info );
214212 uint8 phase = (req_params [1 ] >> 8 ) & 0x0f ;
215213 uint16 block = ((req_params [1 ] >> 24 ) & 0xff ) | ((req_params [1 ] >> 16 ) & 0xff ) << 8 ;
216214 uint8 * buff = (uint8 * )& req_params [2 ];
217215
218216#if _FS_READONLY == 0
217+ uint16 block_size = STORAGE_FUNC_BLOCK_SIZE (device_info );
218+ uint8 phase_count = STORAGE_FUNC_WRITE_PHASE_COUNT (device_info );
219219 int offset = (block * block_size ) + ((block_size / phase_count ) * phase );
220220 lseek (vmu_fd , offset , SEEK_SET );
221221 int res = write (vmu_fd , buff , (block_size / phase_count ));
@@ -345,17 +345,19 @@ static void maple_cmd_proc(int8 cmd, maple_frame_t *req, maple_frame_t *resp) {
345345}
346346#endif // MAPLE_SNIFFER
347347
348- static void maple_dma_proc () {
348+ static void maple_dma_proc (int is_request ) {
349349 uint32 * data , * recv_data , addr , value ;
350350 uint32 trans_count ;
351351 uint8 len , last = 0 , port , pattern ;
352352 maple_frame_t req_frame ;
353353 maple_frame_t * resp_frame_ptr ;
354354
355355 addr = MAPLE_REG (MAPLE_DMA_ADDR );
356-
357356 data = (uint32 * )NONCACHED_ADDR (addr );
358357
358+ /* TODO: Support to prevent command sending to physical VMU. */
359+ (void )is_request ;
360+
359361 for (trans_count = 0 ; trans_count < 24 && !last ; ++ trans_count ) {
360362
361363 /* First word: transfer parameters */
@@ -393,8 +395,12 @@ static void maple_dma_proc() {
393395
394396 maple_frame_t resp_frame ;
395397 maple_read_frame (recv_data , & resp_frame );
396- maple_dump_frame ("SEND" , trans_count , & req_frame );
397- maple_dump_frame ("RECV" , trans_count , & resp_frame );
398+ if (is_request ) {
399+ maple_dump_frame ("SEND" , trans_count , & req_frame );
400+ }
401+ else {
402+ maple_dump_frame ("RECV" , trans_count , & resp_frame );
403+ }
398404
399405 maple_cmd_proc (req_frame .cmd , & req_frame , resp_frame_ptr );
400406
@@ -426,9 +432,11 @@ static void *maple_dma_handler(void *passer, register_stack *stack, void *curren
426432
427433 if (passer == current_vector ) {
428434 // Handle UBC break on Maple register
435+ maple_dma_proc (1 );
429436 requested = 1 ;
430- } else if (requested ) {
431- maple_dma_proc ();
437+ }
438+ else if (requested ) {
439+ maple_dma_proc (0 );
432440 requested = 0 ;
433441 }
434442#else
@@ -438,7 +446,7 @@ static void *maple_dma_handler(void *passer, register_stack *stack, void *curren
438446 || ((* ASIC_IRQ9_MASK & ASIC_NRM_MAPLE_DMA ) && code == EXP_CODE_INT9 )
439447 || ((* ASIC_IRQ13_MASK & ASIC_NRM_MAPLE_DMA ) && code == EXP_CODE_INT13 )
440448 ) {
441- maple_dma_proc ();
449+ maple_dma_proc (0 );
442450 }
443451#endif
444452 return current_vector ;
@@ -448,8 +456,11 @@ static void *maple_dma_handler(void *passer, register_stack *stack, void *curren
448456int maple_init_irq () {
449457
450458#ifdef HAVE_UBC
459+ LOGFF ("with UBC\n" );
451460 ubc_init ();
452461 ubc_configure_channel (UBC_CHANNEL_A , MAPLE_DMA_STATUS , UBC_BBR_OPERAND | UBC_BBR_WRITE );
462+ #else
463+ LOGFF ("without UBC\n" );
453464#endif
454465
455466#ifndef NO_ASIC_LT
0 commit comments