WIP for power pin placement on arbiatary padring/package

Author: robtaylor

chipflow_lib/__init__.py

@@ -11,7 +11,7 @@
 from typing import TYPE_CHECKING
 
 if TYPE_CHECKING:
-    from .config_models import Config
+    from ._config_models import Config
 
 __version__ = importlib.metadata.version("chipflow_lib")
 

chipflow_lib/_appresponse.py

@@ -0,0 +1,39 @@
+from dataclasses import dataclass
+
+from pydantic import BaseModel, PlainSerializer, model_serializer
+
+@dataclass
+class OmitIfNone:
+    pass
+
+class AppResponseModel(BaseModel):
+    @model_serializer
+    def _serialize(self):
+        skip_if_none = set()
+        serialize_aliases = dict()
+
+        # Gather fields that should omit if None
+        for name, field_info in self.model_fields.items():
+            if any(
+                isinstance(metadata, OmitIfNone) for metadata in field_info.metadata
+            ):
+                skip_if_none.add(name)
+            elif field_info.serialization_alias:
+                serialize_aliases[name] = field_info.serialization_alias
+
+        serialized = dict()
+
+        for name, value in self:
+            # Skip serializing None if it was marked with "OmitIfNone"
+            if value is None and name in skip_if_none:
+                continue
+            serialize_key = serialize_aliases.get(name, name)
+
+            # Run Annotated PlainSerializer
+            for metadata in self.model_fields[name].metadata:
+                if isinstance(metadata, PlainSerializer):
+                    value = metadata.func(value)
+
+            serialized[serialize_key] = value
+
+        return serialized

chipflow_lib/_config_models.py

@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: BSD-2-Clause
+from typing import Dict, Optional, Literal, Any, List
+
+from pydantic import BaseModel
+
+from .platforms._utils import Process, PowerConfig
+
+Voltage = float
+
+class SiliconConfig(BaseModel):
+    """Configuration for silicon in chipflow.toml."""
+    process: 'Process'
+    package: Literal["caravel", "cf20", "pga144"]
+    power: Dict[str, Voltage] = {}
+    debug: Optional[Dict[str, bool]] = None
+
+# TODO: add validation that top components, clock domains and power domains
+#       not begin with '_' (unless power domain _core)
+class ChipFlowConfig(BaseModel):
+    """Root configuration for chipflow.toml."""
+    project_name: str
+    top: Dict[str, Any] = {}
+    steps: Optional[Dict[str, str]] = None
+    silicon: Optional[SiliconConfig] = None
+    clock_domains: Optional[List[str]] = None
+    power: Optional[PowerConfig] = None
+
+
+class Config(BaseModel):
+    """Root configuration model for chipflow.toml."""
+    chipflow: ChipFlowConfig

chipflow_lib/config.py

@@ -6,7 +6,7 @@
 from pydantic import ValidationError
 
 from . import ChipFlowError
-from .config_models import Config
+from ._config_models import Config
 
 def get_dir_models():
     return os.path.dirname(__file__) + "/models"

chipflow_lib/config_models.py

@@ -6,7 +6,7 @@
 from pprint import pformat
 
 from . import _parse_config, _ensure_chipflow_root, ChipFlowError
-from .platforms import top_components, LockFile, PACKAGE_DEFINITIONS
+from .platforms._utils import top_components, LockFile, PACKAGE_DEFINITIONS
 
 # logging.basicConfig(stream=sys.stdout, level=logging.DEBUG)
 logger = logging.getLogger(__name__)
@@ -41,7 +41,7 @@ def lock_pins() -> None:
     for name, component in top.items():
         package_def.register_component(name, component)
 
-    newlock = package_def.allocate_pins(config, process, oldlock)
+    newlock = package_def._allocate_pins(config, process, oldlock)
 
     with open(lockfile, 'w') as f:
         f.write(newlock.model_dump_json(indent=2, serialize_as_any=True))

chipflow_lib/pin_lock.py

@@ -8,13 +8,18 @@
 
 from .silicon import *
 from .sim import *
-from .utils import *
+from ._utils import (
+        IO_ANNOTATION_SCHEMA, IOSignature, IOModel,
+        OutputIOSignature, InputIOSignature, BidirIOSignature,
+        PACKAGE_DEFINITIONS, Process,
+        GAPackageDef, QuadPackageDef, BareDiePackageDef,
+        BringupPins, JTAGPins, PowerPins
+)
 
 __all__ = ['IO_ANNOTATION_SCHEMA', 'IOSignature', 'IOModel',
            'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',
-           'load_pinlock', "PACKAGE_DEFINITIONS", 'top_components', 'LockFile',
-           'Package', 'PortMap', 'Port', 'Process',
-           'GAPackageDef', 'QuadPackageDef', 'BareDiePackageDef', 'BasePackageDef',
+           'PACKAGE_DEFINITIONS', 'Process',
+           'GAPackageDef', 'QuadPackageDef', 'BareDiePackageDef',
            'BringupPins', 'JTAGPins', 'PowerPins',
            'SiliconPlatformPort', 'SiliconPlatform',
            'SimPlatform']